diff --git a/cpu/samd21/cpu.c b/cpu/samd21/cpu.c
index f6c59bccb..9590e9fcc 100644
--- a/cpu/samd21/cpu.c
+++ b/cpu/samd21/cpu.c
@@ -161,11 +161,10 @@ static void clk_init(void)
     }
 
     SYSCTRL->DFLLCTRL.bit.ENABLE = 1;
-    while ((SYSCTRL->PCLKSR.reg & (SYSCTRL_PCLKSR_DFLLRDY |
-                                   SYSCTRL_PCLKSR_DFLLLCKF |
-                                   SYSCTRL_PCLKSR_DFLLLCKC)) == 0) {
-        /* Wait for DFLLLXXX sync */
-    }
+    uint32_t mask = SYSCTRL_PCLKSR_DFLLRDY |
+                    SYSCTRL_PCLKSR_DFLLLCKF |
+                    SYSCTRL_PCLKSR_DFLLLCKC;
+    while ((SYSCTRL->PCLKSR.reg & mask) != mask) { } /* Wait for DFLL lock */
 
     /* select the DFLL as source for clock generator 0 (CPU core clock) */
     GCLK->GENDIV.reg =  (GCLK_GENDIV_DIV(1U) | GCLK_GENDIV_ID(0));