diff --git a/boards/cc3200-launchxl/include/periph_conf.h b/boards/cc3200-launchxl/include/periph_conf.h index 73d59d005..75951c919 100644 --- a/boards/cc3200-launchxl/include/periph_conf.h +++ b/boards/cc3200-launchxl/include/periph_conf.h @@ -59,15 +59,14 @@ static const spi_conf_t spi_config[] = { .gpio_port = 0, .pins = (spi_pins_t){ .miso = 05, .sck = 04, .mosi = 06, .cs = 07 }, .config = (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | - SPI_CS_ACTIVELOW | SPI_WL_8 | PRCM_RUN_MODE_CLK), + SPI_CS_ACTIVELOW | SPI_WL_8), }, { .base_addr = LSPI_BASE, .gpio_port = 1, .pins = (spi_pins_t){ .miso = 0, .sck = 0, .mosi = 0, .cs = 0 }, .config = (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF | - SPI_CS_ACTIVEHIGH | SPI_WL_32 | PRCM_RUN_MODE_CLK | - PRCM_SLP_MODE_CLK), + SPI_CS_ACTIVEHIGH | SPI_WL_32), } }; diff --git a/cpu/cc3200/periph/spi.c b/cpu/cc3200/periph/spi.c index 6fa3047d9..7e675b2fd 100644 --- a/cpu/cc3200/periph/spi.c +++ b/cpu/cc3200/periph/spi.c @@ -173,9 +173,12 @@ void spi_init(spi_t bus) } /* enable/configure SPI clock */ - (*cc3200_arcm_reg_t)(&ARCM->MCSPI_A1 + bus * - 0x1C)->clk_gating |= spi_config[bus].config & - PRCM_MODE_CLK_MASK; + if (spi(bus) == GSPI_BASE) { + ARCM->MCSPI_A1.clk_gating |= PRCM_RUN_MODE_CLK; + } + else if (spi(bus) == LSPI_BASE) { + ARCM->MCSPI_A2.clk_gating |= PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK; + } /* reset spi for the changes to take effect */ spi_reset(bus); @@ -227,7 +230,8 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, const void *out, spi(bus)->ch0_conf |= MCSPI_CH0CONF_FORCE; /* perform transfer */ - if (ROM_SPITransfer((uint32_t)spi(bus), (uint8_t *)out, (uint8_t *)in, len, + if (ROM_SPITransfer((uint32_t)spi(bus), (uint8_t *)out, (uint8_t *)in, + len, 0) != SPI_OK) { DEBUG("SPI: Transfer failed \n"); /* check that len and word length combination is valid */