diff --git a/cpu/stm32_common/dist/clk_conf/clk_conf.c b/cpu/stm32_common/dist/clk_conf/clk_conf.c index 12b4f24cc..80fa2b827 100644 --- a/cpu/stm32_common/dist/clk_conf/clk_conf.c +++ b/cpu/stm32_common/dist/clk_conf/clk_conf.c @@ -300,9 +300,8 @@ int main(int argc, char **argv) bool use_alt_48MHz = false; unsigned clock_48MHz = cfg->need_48MHz ? 48000000U : 0; - if ((cfg->family == 0 || cfg->family == 1) && pll_src == HSI) { - /* HSI / 2 is used as source */ - m = 2; + if ((cfg->hsi_prediv) && (pll_src == HSI)) { + m = cfg->hsi_prediv; } /* main PLL */ diff --git a/cpu/stm32_common/dist/clk_conf/clk_conf.h b/cpu/stm32_common/dist/clk_conf/clk_conf.h index aad61f677..06b37b921 100644 --- a/cpu/stm32_common/dist/clk_conf/clk_conf.h +++ b/cpu/stm32_common/dist/clk_conf/clk_conf.h @@ -68,6 +68,17 @@ enum { STM32F215, STM32F217, + STM32F301, + STM32F302, + STM32F303, + STM32F334, + STM32F373, + STM32F318, + STM32F328, + STM32F358, + STM32F378, + STM32F398, + STM32F401, STM32F405, STM32F407, @@ -167,6 +178,8 @@ typedef struct { bool has_pll_sai_m; /**< PLL SAI has a M factor */ bool has_pll_i2s_alt_input; /**< PLL I2S has an external input available */ + unsigned hsi_prediv; /**< Value if HSI has a fixed prediv, 0 otherwise */ + int has_alt_48MHz; /**< 48MHz can be generated by an alternate source */ bool need_48MHz; /**< 48MHz is needed */ } clk_cfg_t; @@ -212,6 +225,17 @@ static const unsigned stm32_model[] = { STM32F(215), STM32F(217), + STM32F(301), + STM32F(302), + STM32F(303), + STM32F(334), + STM32F(373), + STM32F(318), + STM32F(328), + STM32F(358), + STM32F(378), + STM32F(398), + STM32F(401), STM32F(405), STM32F(407), @@ -309,6 +333,7 @@ static const clk_cfg_t stm32_clk_cfg[] = { .has_pll_sai = false, .has_pll_i2s_alt_input = false, .has_alt_48MHz = 0, + .hsi_prediv = 2, .need_48MHz = false, }, [STM32F100] = { @@ -336,6 +361,7 @@ static const clk_cfg_t stm32_clk_cfg[] = { .has_pll_sai = false, .has_pll_i2s_alt_input = false, .has_alt_48MHz = 0, + .hsi_prediv = 2, .need_48MHz = false, }, [STM32F101 ... STM32F103] = { @@ -363,6 +389,7 @@ static const clk_cfg_t stm32_clk_cfg[] = { .has_pll_sai = false, .has_pll_i2s_alt_input = false, .has_alt_48MHz = 0, + .hsi_prediv = 2, .need_48MHz = false, }, [STM32F205 ... STM32F217] = { @@ -378,6 +405,34 @@ static const clk_cfg_t stm32_clk_cfg[] = { .has_alt_48MHz = 0, .need_48MHz = true, }, + [STM32F301 ... STM32F398] = { + .family = STM32F3, + .max_coreclock = 72000000U, + .max_apb1 = 36000000U, + .max_apb2 = 72000000U, + .hsi = 8000000U, + .pll = { + .min_vco_input = 1000000U, + .max_vco_input = 25000000U, + .min_vco_output = 1000000U, + .max_vco_output = 72000000U, + .min_m = 1, + .max_m = 16, + .inc_m = 1, + .min_n = 2, + .max_n = 16, + .inc_n = 1, + .min_p = 1, + .max_p = 1, + .inc_p = 1, + }, + .has_pll_i2s = false, + .has_pll_sai = false, + .has_pll_i2s_alt_input = false, + .has_alt_48MHz = 0, + .hsi_prediv = 2, + .need_48MHz = false, + }, [STM32F401] = { .family = STM32F4, .max_coreclock = 84000000U, diff --git a/cpu/stm32_common/stmclk.c b/cpu/stm32_common/stmclk.c index 96f7e75a1..fc8454d0e 100644 --- a/cpu/stm32_common/stmclk.c +++ b/cpu/stm32_common/stmclk.c @@ -19,7 +19,8 @@ * @} */ -#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) +#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F2) \ + || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) #include "cpu.h" #include "stmclk.h" @@ -40,6 +41,7 @@ * @name PLL configuration * @{ */ +#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) /* figure out which input to use */ #if (CLOCK_HSE) #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE @@ -89,19 +91,54 @@ #define PLL_M (CLOCK_PLL_M << RCC_PLLCFGR_PLLM_Pos) #define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos) #define PLL_Q (CLOCK_PLL_Q << RCC_PLLCFGR_PLLQ_Pos) + +#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) +#if (CLOCK_HSE) +#define PLL_SRC (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1) +#else +#define PLL_SRC (RCC_CFGR_PLLSRC_HSI_DIV2) +#endif + +#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18) +#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1) + +#if defined(CPU_FAM_STM32F0) +#define CLOCK_APB2_DIV (0) +#endif + +#elif defined(CPU_FAM_STM32F1) +#if CLOCK_HSE +#define PLL_SRC (RCC_CFGR_PLLSRC) /* HSE */ +#else +#define PLL_SRC (0) /* HSI / 2 */ +#endif + +#define PLL_MUL ((CLOCK_PLL_MUL - 2) << 18) +#define PLL_PREDIV (CLOCK_PLL_PREDIV - 1) + +#define RCC_CR_HSITRIM_4 (1 << 7) +#define RCC_CFGR_PLLMUL RCC_CFGR_PLLMULL + +#endif /** @} */ /** * @name Deduct the needed flash wait states from the core clock frequency * @{ */ +#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(STM32F3) +#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U) +#else #define FLASH_WAITSTATES (CLOCK_CORECLOCK / 30000000U) +#endif /* we enable I+D cashes, pre-fetch, and we set the actual number of * needed flash wait states */ #if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) #define FLASH_ACR_CONFIG (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES) #elif defined(CPU_FAM_STM32F7) #define FLASH_ACR_CONFIG (FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | FLASH_WAITSTATES) +#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3) +#define FLASH_ACR_CONFIG (FLASH_ACR_PRFTBE | FLASH_WAITSTATES) #endif /** @} */ @@ -150,7 +187,19 @@ void stmclk_init_sysclk(void) RCC->DCKCFGR2 |= RCC_DCKCFGR2_CK48MSEL; #endif /* now we can safely configure and start the PLL */ +#if defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_P | PLL_Q); +#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || defined(CPU_FAM_STM32F3) + /* reset PLL configuration bits */ + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL); + /* set PLL configuration */ + RCC->CFGR |= PLL_SRC | PLL_MUL; +#if CLOCK_PLL_PREDIV == 2 + RCC->CFGR |= RCC_CFGR_PLLXTPRE; /* PREDIV == 2 */ +#elif CLOCK_PLL_PREDIV > 2 + RCC->CFGR2 = PLL_PREDIV; /* PREDIV > 2 */ +#endif +#endif RCC->CR |= (RCC_CR_PLLON); while (!(RCC->CR & RCC_CR_PLLRDY)) {} @@ -176,4 +225,6 @@ void stmclk_init_sysclk(void) } #else typedef int dont_be_pedantic; -#endif /* defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */ +#endif /* defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || + * defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F3) || + * defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) */ diff --git a/cpu/stm32f0/cpu.c b/cpu/stm32f0/cpu.c index 88884d123..1737da2e5 100644 --- a/cpu/stm32f0/cpu.c +++ b/cpu/stm32f0/cpu.c @@ -18,34 +18,9 @@ */ #include "cpu.h" -#include "periph_conf.h" +#include "stmclk.h" #include "periph/init.h" -/* Check the source to be used for the PLL */ -#if defined(CLOCK_HSI) && defined(CLOCK_HSE) -#error "Only provide one of two CLOCK_HSI/CLOCK_HSE" -#elif CLOCK_HSI -#define CLOCK_CR_SOURCE RCC_CR_HSION -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY -#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_DIV2) -#define CLOCK_PLL_MUL_MUL 2 -#define CLOCK_DISABLE_HSI 0 - -#if (RCC_PLL_MUL * RCC_PLL_MUL_MUL) > 6 -#error PLL with HSI as clock source cant extend 6 times multiplier -#endif -#elif CLOCK_HSE -#define CLOCK_CR_SOURCE RCC_CR_HSEON -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY -#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1) -#define CLOCK_PLL_MUL_MUL 1 -#define CLOCK_DISABLE_HSI 1 -#else -#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h" -#endif - -static void clock_init(void); - /** * @brief Initialize the CPU, set IRQ priorities */ @@ -54,82 +29,7 @@ void cpu_init(void) /* initialize the Cortex-M core */ cortexm_init(); /* initialize the clock system */ - clock_init(); + stmclk_init_sysclk(); /* trigger static peripheral initialization */ periph_init(); } - -/** - * @brief Configure the controllers clock system - * - * The clock initialization make the following assumptions: - * - the external HSE clock from an external oscillator is used as base clock - * - the internal PLL circuit is used for clock refinement - * - * Use the following formulas to calculate the needed values: - * - * SYSCLK = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_P - * USB, SDIO and RNG Clock = ((HSE_VALUE / CLOCK_PLL_M) * CLOCK_PLL_N) / CLOCK_PLL_Q - * - * The actual used values are specified in the board's `periph_conf.h` file. - * - * NOTE: currently there is not timeout for initialization of PLL and other locks - * -> when wrong values are chosen, the initialization could stall - */ -static void clock_init(void) -{ - /* reset clock configuration register */ - RCC->CFGR = 0; - RCC->CFGR2 = 0; - - /* disable HSE, CSS and PLL */ - RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); - - /* disable all clock interrupts */ - RCC->CIR = 0; - - /* enable the high speed clock source */ - RCC->CR |= CLOCK_CR_SOURCE; - - /* wait for the high speed clock to be ready */ - while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {} - - /* setup the peripheral bus prescalers */ - - /* set HCLK = SYSCLK, so no clock division here */ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - /* set PCLK = HCLK, so its not divided */ - RCC->CFGR |= RCC_CFGR_PPRE_DIV1; - - /* configure the PLL */ - - /* reset PLL configuration bits */ - RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL); - /* set PLL configuration */ - RCC->CFGR |= CLOCK_PLL_SOURCE | ((((CLOCK_PLL_MUL * CLOCK_PLL_MUL_MUL) - 2) & 0xf) << 18); - - /* enable PLL again */ - RCC->CR |= RCC_CR_PLLON; - /* wait until PLL is stable */ - while(!(RCC->CR & RCC_CR_PLLRDY)) {} - - /* configure flash latency */ - - /* enable pre-fetch buffer and set flash latency to 1 cycle*/ - FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; - - /* configure the sysclock and the peripheral clocks */ - - /* set sysclock to be driven by the PLL clock */ - RCC->CFGR &= ~RCC_CFGR_SW; - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* wait for sysclock to be stable */ - while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {} - -#if CLOCK_DISABLE_HSI - /* disable the HSI if we use the HSE */ - RCC->CR &= ~(RCC_CR_HSION); - while (RCC->CR & RCC_CR_HSIRDY) {} -#endif -} diff --git a/cpu/stm32f1/stmclk.c b/cpu/stm32f1/stmclk.c deleted file mode 100644 index 534e4787f..000000000 --- a/cpu/stm32f1/stmclk.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (C) 2017 Freie Universität Berlin - * - * This file is subject to the terms and conditions of the GNU Lesser - * General Public License v2.1. See the file LICENSE in the top level - * directory for more details. - */ - -/** - * @ingroup cpu_stm32f1 - * @{ - * - * @file - * @brief Implementation of STM32F1 clock configuration - * - * @author Stefan Pfeiffer - * @author Alaeddine Weslati - * @author Thomas Eichinger - * @author Hauke Petersen - * @author Nick van IJzendoorn - * @author Víctor Ariño - * - * @} - */ - -#include "irq.h" -#include "cpu.h" -#include "stmclk.h" -#include "periph_conf.h" - -/* make sure we have all needed information about the clock configuration */ -#ifndef CLOCK_HSE -#error "Please provide CLOCK_HSE in your board's perhip_conf.h" -#endif -#ifndef CLOCK_LSE -#error "Please provide CLOCK_LSE in your board's periph_conf.h" -#endif -#ifndef CLOCK_CORECLOCK -#error "Please provide CLOCK_CORECLOCK in your board's periph_conf.h" -#endif -#if !defined(CLOCK_PLL_MUL) || !defined(CLOCK_PLL_DIV) -#error "Please provide a valid PLL configuration in your board's periph_conf.h" -#endif -#if !defined(CLOCK_AHB_DIV) || !defined(CLOCK_AHB) || \ - !defined(CLOCK_APB1_DIV) || !defined(CLOCK_APB1) || \ - !defined(CLOCK_APB2_DIV) || !defined(CLOCK_APB2) -#error "Please provide a AHB and APBx configuration in your board configuration" -#endif - -/* make sure the selected system clock is valid */ -#if (CLOCK_CORECLOCK > 72000000) -#error "clock config: the selected system clock exceeds 72MHz" -#endif - -/* figure out which base block to use */ -#if CLOCK_HSE -#if (CLOCK_HSE < 4000000) || (CLOCK_HSE > 16000000) -#error "clock config: HSE value is out of valid range" -#endif -#define BASECLK (CLOCK_HSE) -#else -#define BASECLK (8000000) /* HSI is alway 8MHz */ -#endif - -/* if PLL is configured, verify its parameters */ -#if (CLOCK_PLL_DIV && CLOCK_PLL_MUL) -#define USEPLL -/* check clock config */ -#if (CLOCK_CORECLOCK != ((BASECLK / CLOCK_PLL_DIV) * CLOCK_PLL_MUL)) -#error "clock config: PLL configuration does not yield expected system clock" -#endif -/* make sure PLL_MUL is in range */ -#if (CLOCK_PLL_MUL < 2) || (CLOCK_PLL_MUL > 17) -#error "clock config: CLOCK_PLL_MUL is out of range" -#endif -/* make sure PLL_DIV is 2 when using HSI as input */ -#if (!CLOCK_HSE) && (CLOCK_PLL_DIV != 2) -#error "clock config: CLOCK_PLL_DIV must be 2 when using HSI oscillator" -#endif -/* and produce the actual PLL configuration */ -#if CLOCK_HSE -#define PLLSRC (RCC_CFGR_PLLSRC) -#if (CLOCK_PLL_DIV == 2) -#define PLLDIV (RCC_CFGR_PLLXTPRE) -#else -#define PLLDIV (0) -#endif -#else -#define PLLSRC (0) -#define PLLDIV (0) -#endif -#define PLLMUL ((CLOCK_PLL_MUL - 2) << 18) -/* and join it for writing the the CFGR register */ -#define PLLCFG (PLLMUL | PLLDIV | PLLSRC) -#else -#define PLLCFG (0) -#endif - -/* now we need to select the system clock source configuration */ -#ifdef USEPLL -#define SYSCLK_SRC RCC_CFGR_SW_PLL -#define SYSCLK_BSY RCC_CFGR_SWS_PLL -#elif CLK_HSE -#define SYSCLK_SRC RCC_CFGR_SW_HSE -#define SYSCLK_BSY RCC_CFGR_SWS_HSE -#else -#define SYSCLK_SRC RCC_CFGR_SW_HSI -#define SYSCLK_BSY RCC_CFGR_SWS_HSI -#endif - -/* Configuration of flash access cycles */ -#define FLASH_WAITSTATES ((CLOCK_CORECLOCK - 1) / 24000000U) - -/* define some bitfields */ -#define HSITRIM (1 << 7) -#define SWSHSI (0) - - -void stmclk_init_sysclk(void) -{ - /* disable any IRQs */ - unsigned is = irq_disable(); - RCC->CIR = 0; - - /* enable HSI and use it as system clock */ - stmclk_enable_hsi(); - RCC->CFGR &= ~(RCC_CFGR_SW); - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {} - - /* its safe now to program the flash wait states */ - FLASH->ACR = (FLASH_ACR_PRFTBE | FLASH_WAITSTATES); - /* now we are in a defined state and can stop all other clocks */ - RCC->CR = (HSITRIM | RCC_CR_HSION); - /* next we put in the desired PLL and peripheral bus configuration */ - RCC->CFGR = (CLOCK_AHB_DIV | CLOCK_APB1_DIV | CLOCK_APB2_DIV | PLLCFG); - - /* now we need to (re-)enable the used clocks */ -#if CLOCK_HSE - RCC->CR |= RCC_CR_HSEON; - while (!(RCC->CR & RCC_CR_HSERDY)) {} -#endif -#ifdef USEPLL - RCC->CR |= RCC_CR_PLLON; - while (!(RCC->CR & RCC_CR_PLLRDY)) {} -#endif - - /* leaves switching the system clock */ - RCC->CFGR |= SYSCLK_SRC; - while ((RCC->CFGR & RCC_CFGR_SWS) != SYSCLK_BSY) {} - - /* disable HSI (if not used) */ - stmclk_disable_hsi(); - - /* re-enable IRQs */ - irq_restore(is); -} diff --git a/cpu/stm32f3/cpu.c b/cpu/stm32f3/cpu.c index e6f99ece3..a9fa456b7 100644 --- a/cpu/stm32f3/cpu.c +++ b/cpu/stm32f3/cpu.c @@ -18,36 +18,9 @@ * @} */ -#include #include "cpu.h" -#include "periph_conf.h" #include "periph/init.h" - -/* Check the source to be used for the PLL */ -#if defined(CLOCK_HSI) && defined(CLOCK_HSE) -#error "Only provide one of two CLOCK_HSI/CLOCK_HSE" -#elif CLOCK_HSI -#define CLOCK_CR_SOURCE RCC_CR_HSION -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSIRDY -#ifdef RCC_CFGR_PLLSRC_HSI_DIV2 -#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_DIV2) -#define CLOCK_PLL_MUL_MULTIPLIER 2 -#else -#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSI_PREDIV) -#define CLOCK_PLL_MUL_MULTIPLIER 1 -#endif -#define CLOCK_DISABLE_HSI 0 -#elif CLOCK_HSE -#define CLOCK_CR_SOURCE RCC_CR_HSEON -#define CLOCK_CR_SOURCE_RDY RCC_CR_HSERDY -#define CLOCK_PLL_SOURCE (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1) -#define CLOCK_PLL_MUL_MULTIPLIER 1 -#define CLOCK_DISABLE_HSI 1 -#else -#error "Please provide CLOCK_HSI or CLOCK_HSE in boards/NAME/includes/perhip_cpu.h" -#endif - -static void cpu_clock_init(void); +#include "stmclk.h" /** * @brief Initialize the CPU, set IRQ priorities @@ -57,98 +30,7 @@ void cpu_init(void) /* initialize the Cortex-M core */ cortexm_init(); /* initialize the clock system */ - cpu_clock_init(); + stmclk_init_sysclk(); /* trigger static peripheral initialization */ periph_init(); } - -/** - * @brief Configure the controllers clock system - * - * The clock initialization make the following assumptions: - * - the HSI and HSE selection is based on the CLOCK_HSI or CLOCK_HSE define in the periph_conf.h - * - the internal PLL circuit is used for clock refinement - * - * The actual used values are specified in the board's `periph_conf.h` file. - * - * NOTE: currently there is not timeout for initialization of PLL and other locks - * -> when wrong values are chosen, the initialization could stall - */ -static void cpu_clock_init(void) -{ - /* configure the high speed clock */ - - /* reset clock configuration register */ - RCC->CFGR = 0; - - /* disable HSE, CSS and PLL */ - RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); - - /* disable all clock interrupts */ - RCC->CIR = 0; - - /* enable the high speed clock */ - RCC->CR |= CLOCK_CR_SOURCE; - - /* wait for high speed clock to be ready */ - while (!(RCC->CR & CLOCK_CR_SOURCE_RDY)) {} - - /* setup the peripheral bus prescalers */ - - /* set the AHB clock divider */ - RCC->CFGR &= ~RCC_CFGR_HPRE; - RCC->CFGR |= CLOCK_AHB_DIV; - /* set the APB2 (high speed) bus clock divider */ - RCC->CFGR &= ~RCC_CFGR_PPRE2; - RCC->CFGR |= CLOCK_APB2_DIV; - /* set the APB1 (low speed) bus clock divider */ - RCC->CFGR &= ~RCC_CFGR_PPRE1; - RCC->CFGR |= CLOCK_APB1_DIV; - - /* configure the PLL */ - - /* reset PLL configuration */ - RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL); - /* set PLL to use high speed clock with prescaler 1 as input */ - RCC->CFGR |= CLOCK_PLL_SOURCE | ((((CLOCK_PLL_MUL * CLOCK_PLL_MUL_MULTIPLIER) - 2) & 0xf) << 18); - - /* enable PLL again */ - RCC->CR |= RCC_CR_PLLON; - /* wait until PLL is stable */ - while(!(RCC->CR & RCC_CR_PLLRDY)) {} - - /* configure flash latency */ - - /* reset flash access control register */ - FLASH->ACR = 0; - /* enable pre-fetch buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - /* set flash latency */ - FLASH->ACR &= ~FLASH_ACR_LATENCY; - FLASH->ACR |= CLOCK_FLASH_LATENCY; - - /* configure the sysclock and the peripheral clocks */ - - /* set sysclock to be driven by the PLL clock */ - RCC->CFGR &= ~RCC_CFGR_SW; - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* wait for sysclock to be stable */ - while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {} - -#if CLOCK_DISABLE_HSI - /* disable the HSI if we use the HSE */ - RCC->CR &= ~(RCC_CR_HSION); - while (RCC->CR & RCC_CR_HSIRDY) {} - - /* swith I2Cx clock source to SYSCLK */ - RCC->CFGR3 &= ~(RCC_CFGR3_I2CSW); - RCC->CFGR3 |= RCC_CFGR3_I2C1SW_SYSCLK; -#ifdef RCC_CFGR3_I2C2SW_SYSCLK - RCC->CFGR3 |= RCC_CFGR3_I2C2SW_SYSCLK; -#endif -#ifdef RCC_CFGR3_I2C3SW_SYSCLK - RCC->CFGR3 |= RCC_CFGR3_I2C3SW_SYSCLK; -#endif -#endif -}