diff --git a/boards/nucleo-f722ze/Makefile.features b/boards/nucleo-f722ze/Makefile.features
index 58a41a2a2..450d4e45b 100644
--- a/boards/nucleo-f722ze/Makefile.features
+++ b/boards/nucleo-f722ze/Makefile.features
@@ -5,6 +5,9 @@ FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot
+
 # load the common Makefile.features for Nucleo144 boards
 include $(RIOTBOARD)/common/nucleo144/Makefile.features
 
diff --git a/boards/nucleo-f746zg/Makefile.features b/boards/nucleo-f746zg/Makefile.features
index e3a775878..e65470794 100644
--- a/boards/nucleo-f746zg/Makefile.features
+++ b/boards/nucleo-f746zg/Makefile.features
@@ -5,6 +5,9 @@ FEATURES_PROVIDED += periph_rtt
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot
+
 # load the common Makefile.features for Nucleo boards
 include $(RIOTBOARD)/common/nucleo144/Makefile.features
 
diff --git a/boards/nucleo-f767zi/Makefile.features b/boards/nucleo-f767zi/Makefile.features
index 1fec6ceb1..b6502bf99 100644
--- a/boards/nucleo-f767zi/Makefile.features
+++ b/boards/nucleo-f767zi/Makefile.features
@@ -8,6 +8,9 @@ FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
 FEATURES_PROVIDED += periph_eth
 
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot
+
 # load the common Makefile.features for Nucleo boards
 include $(RIOTBOARD)/common/nucleo144/Makefile.features
 
diff --git a/cpu/stm32f7/Makefile.include b/cpu/stm32f7/Makefile.include
index 2e32400dd..d3a25f6ba 100644
--- a/cpu/stm32f7/Makefile.include
+++ b/cpu/stm32f7/Makefile.include
@@ -1,5 +1,28 @@
 export CPU_ARCH = cortex-m7
 export CPU_FAM  = stm32f7
 
+# STM32F7 uses sectors instead of pages, where the minimum sector length is 16KB or
+# 32kB (the first sector), depending on the CPU_MODEL. Therefore RIOTBOOT_LEN must
+# be 16KB or 32kB to cover a whole sector.
+ifneq (,$(filter stm32f722ze ,$(CPU_MODEL)))
+  RIOTBOOT_LEN ?= 0x4000
+else
+  RIOTBOOT_LEN ?= 0x8000
+endif
+
+# CPU_IRQ_NUMOF for STM32F7 boards is < 110+16 so (126*4 bytes = 504 bytes ~= 0x200)
+# RIOTBOOT_HDR_LEN can be set to 0x200.
+# Details on alignment requirements for M4 in `cpu/cortexm_common/Makefile.include`.
+RIOTBOOT_HDR_LEN ?= 0x200
+
+# Sectors don't have the same length. Per bank there can be up to 12 sectors. If
+# the smallest sector size is 16kb the first 4 sectors are 16kB long, the 5th is
+# 64kB and the remaining 7 are 128kB. Since flash can only be erased by sector,
+# slots can't overlap over sectors.
+# RIOTBOOT_LEN is removed twice, once at the start of the flash for the bootloader,
+# and a second time at the end of the flash, to get evenly sized and distributed slots.
+SLOT0_LEN ?= $(shell printf "0x%x" $$((($(ROM_LEN:%K=%*1024)-2*$(RIOTBOOT_LEN)) / $(NUM_SLOTS))))
+SLOT1_LEN ?= $(SLOT0_LEN)
+
 include $(RIOTCPU)/stm32_common/Makefile.include
 include $(RIOTMAKE)/arch/cortexm.inc.mk
diff --git a/cpu/stm32f7/include/cpu_conf.h b/cpu/stm32f7/include/cpu_conf.h
index 27c456e67..60e1759e5 100644
--- a/cpu/stm32f7/include/cpu_conf.h
+++ b/cpu/stm32f7/include/cpu_conf.h
@@ -43,6 +43,7 @@ extern "C" {
 #elif defined(CPU_LINE_STM32F722xx)
 #define CPU_IRQ_NUMOF                   (104U)
 #endif
+#define CPU_FLASH_BASE                  FLASH_BASE
 /** @} */
 
 #ifdef __cplusplus