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cc3200: driverlib removal work in progress

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This commit is contained in:
Wlad Meixner 2019-07-13 16:58:53 +02:00
parent 216a282b47
commit a1475a40c0
24 changed files with 2342 additions and 1983 deletions
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2
boards/cc3200-launchxl/board.c
View File

@ -47,7 +47,7 @@ void led_init(void) {
//
// Enable Peripheral Clocks
//
MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK);
ARCM->GPIO_A.clk_gating |= PRCM_RUN_MODE_CLK;
// enable leads and clear them
gpio_init(LED_RED, GPIO_OUT);

158
cpu/cc3200/cpu.c
View File

@ -1,39 +1,133 @@
#include "cpu.h"
#include "vendor/hw_ints.h"
#include "periph_cpu.h"
#include "periph/init.h"
#include "periph_cpu.h"
#include "vendor/hw_hib3p3.h"
#include "vendor/hw_ints.h"
#include "vendor/hw_types.h"
void cpu_init(void)
{
/* initializes the Cortex-M core */
cortexm_init();
/* init board */
PRCMCC3200MCUInit();
/* 1 priority group */
ROM_IntPriorityGroupingSet(0);
/* trigger static peripheral initialization */
periph_init();
/**
* @brief wait for 3 * count cpu cicles
*
*/
void __attribute__((naked)) delay(unsigned long count) {
__asm(" subs r0, #1\n"
" bne delay\n"
" bx lr");
}
// void periph_clk_enable(unsigned long ulPeripheral, unsigned long ulClkFlags)
// {
// //
// // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC
// // as it is a dummy define for pinmux utility code generation
// //
// if(ulPeripheral != PRCM_ADC)
// {
// HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags;
// }
/**
* @brief init peripheria clock and perform a softreset
*
* @param reg pointer to register
*/
void init_periph_clk(cc3200_periph_regs_t *reg) {
volatile unsigned long ulDelay;
// enable & reset periphiria
reg->soft_reset |= PRCM_SOFT_RESET;
// //
// // Set the default clock for camera
// //
// if(ulPeripheral == PRCM_CAMERA)
// {
// HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404;
// }
// }
// wait for the hardware to perform reset
for (ulDelay = 0; ulDelay < 16; ulDelay++) {
}
// deassert reset
reg->soft_reset &= ~PRCM_SOFT_RESET;
}
uint32_t get_sys_reset_cause(void) {
uint32_t reset_cause;
uint32_t hiber_status;
// reset read reset status
reset_cause = GPRCM->APPS_RESET_CAUSE & 0xFF;
if (reset_cause == PRCM_POWER_ON) {
hiber_status = HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS);
// FIXME: wait for some reason test if this is needed
delay((80 * 200) / 3);
if (hiber_status & 0x1) {
return PRCM_HIB_EXIT;
}
}
return reset_cause;
}
void prcm_fake_for_riot(void) {
cc3200_reg_t tmp;
// DIG DCDC LPDS ECO Enable
HWREG(0x4402F064) |= 0x800000;
// enable hibernate ECO
tmp = HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS);
delay((80 * 200) / 3);
HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0) = tmp | (1 << 4);
delay((80 * 200) / 3);
// enable clock switching
HWREG(0x4402E16C) |= 0x3C;
// enable and reset default periphiria
init_periph_clk(&ARCM->UDMA_A);
// disable udma
ARCM->UDMA_A.clk_gating &= ~PRCM_RUN_MODE_CLK;
if (get_sys_reset_cause() == PRCM_POWER_ON) {
HWREG(0x4402F804) = 0x1;
delay((80 * 200) / 3);
}
//
// SWD mode
//
if (((HWREG(0x4402F0C8) & 0xFF) == 0x2)) {
HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
HWREG(0x4402E114) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
}
//
// Override JTAG mux
//
HWREG(0x4402E184) |= 0x2;
//
// Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1
//
if ((HWREG(0x4402E0A4) & 0xF) == 0x1) {
HWREG(0x4402E0A4) = ((HWREG(0x4402E0A4) & ~0xF));
}
if ((HWREG(0x4402E0A8) & 0xF) == 0x1) {
HWREG(0x4402E0A8) = ((HWREG(0x4402E0A8) & ~0xF));
}
//
// DIG DCDC VOUT trim settings based on PROCESS INDICATOR
//
if (((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) {
HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000)) | (0x32 << 18));
} else {
HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000)) | (0x29 << 18));
}
//
// Enable SOFT RESTART in case of DIG DCDC collapse
//
HWREG(0x4402FC74) &= ~(0x10000000);
//
// Disable the sleep for ANA DCDC
//
HWREG(0x4402F0A8) |= 0x00000004;
}
void cpu_init(void) {
/* initializes the Cortex-M core */
cortexm_init();
/* init board */
prcm_fake_for_riot();
// PRCMCC3200MCUInit();
/* trigger static peripheral initialization */
periph_init();
}

299
cpu/cc3200/driverlib/spi.c
View File

@ -44,24 +44,23 @@
//
//*****************************************************************************
#include "vendor/hw_ints.h"
#include "vendor/hw_types.h"
#include "vendor/hw_memmap.h"
#include "vendor/hw_mcspi.h"
#include "vendor/hw_apps_config.h"
#include "interrupt.h"
#include "spi.h"
#include "interrupt.h"
#include "vendor/hw_apps_config.h"
#include "vendor/hw_ints.h"
#include "vendor/hw_mcspi.h"
#include "vendor/hw_memmap.h"
#include "vendor/hw_types.h"
//*****************************************************************************
//
// A mapping of SPI base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulSPIIntMap[][3] =
{
{SSPI_BASE, INT_SSPI}, // Shared SPI
{GSPI_BASE, INT_GSPI}, // Generic SPI
{LSPI_BASE, INT_LSPI}, // LINK SPI
static const unsigned long g_ppulSPIIntMap[][3] = {
{SSPI_BASE, INT_SSPI}, // Shared SPI
{GSPI_BASE, INT_GSPI}, // Generic SPI
{LSPI_BASE, INT_LSPI}, // LINK SPI
};
//*****************************************************************************
@ -69,11 +68,10 @@ static const unsigned long g_ppulSPIIntMap[][3] =
// A mapping of SPI base address to DMA done interrupt mask bit(s).
//
//*****************************************************************************
static const unsigned long g_ulSPIDmaMaskMap[][2] =
{
{SSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK},
{LSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK},
{GSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK},
static const unsigned long g_ulSPIDmaMaskMap[][2] = {
{SSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK},
{LSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK},
{GSPI_BASE, APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK},
};
//*****************************************************************************
@ -95,8 +93,7 @@ static const unsigned long g_ulSPIDmaMaskMap[][2] =
//*****************************************************************************
static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
unsigned char *ucDin, unsigned long ulCount,
unsigned long ulFlags)
{
unsigned long ulFlags) {
unsigned long ulReadReg;
unsigned long ulWriteReg;
unsigned long ulStatReg;
@ -114,8 +111,7 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//
// Check if output buffer pointer is 0
//
if (ucDout == 0)
{
if (ucDout == 0) {
ulOutIncr = 0;
ulTxDummy = 0xFFFFFFFF;
ucDout = (unsigned char *)&ulTxDummy;
@ -124,8 +120,7 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//
// Check if input buffer pointer is 0
//
if (ucDin == 0)
{
if (ucDin == 0) {
ulInIncr = 0;
ucDin = (unsigned char *)&ulRxDummy;
}
@ -140,18 +135,15 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//
// Enable CS based on Flag
//
if (ulFlags & SPI_CS_ENABLE)
{
if (ulFlags & SPI_CS_ENABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
}
while (ulCount)
{
while (ulCount) {
//
// Wait for space in output register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS)) {
}
//
@ -162,8 +154,7 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//
// Wait for data in input register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS)) {
}
//
@ -186,8 +177,7 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//
// Disable CS based on Flag
//
if (ulFlags & SPI_CS_DISABLE)
{
if (ulFlags & SPI_CS_DISABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
}
@ -215,8 +205,7 @@ static long SPITransfer8(unsigned long ulBase, unsigned char *ucDout,
//*****************************************************************************
static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
unsigned short *usDin, unsigned long ulCount,
unsigned long ulFlags)
{
unsigned long ulFlags) {
unsigned long ulReadReg;
unsigned long ulWriteReg;
unsigned long ulStatReg;
@ -234,8 +223,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Check if count is multiple of half-word
//
if (ulCount % 2)
{
if (ulCount % 2) {
return -1;
}
@ -247,8 +235,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Check if output buffer pointer is 0
//
if (usDout == 0)
{
if (usDout == 0) {
ulOutIncr = 0;
ulTxDummy = 0xFFFFFFFF;
usDout = (unsigned short *)&ulTxDummy;
@ -257,8 +244,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Check if input buffer pointer is 0
//
if (usDin == 0)
{
if (usDin == 0) {
ulInIncr = 0;
usDin = (unsigned short *)&ulRxDummy;
}
@ -273,18 +259,15 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Enable CS based on Flag
//
if (ulFlags & SPI_CS_ENABLE)
{
if (ulFlags & SPI_CS_ENABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
}
while (ulCount)
{
while (ulCount) {
//
// Wait for space in output register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS)) {
}
//
@ -295,8 +278,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Wait for data in input register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS)) {
}
//
@ -319,8 +301,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//
// Disable CS based on Flag
//
if (ulFlags & SPI_CS_DISABLE)
{
if (ulFlags & SPI_CS_DISABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
}
@ -347,8 +328,7 @@ static long SPITransfer16(unsigned long ulBase, unsigned short *usDout,
//*****************************************************************************
static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
unsigned long *ulDin, unsigned long ulCount,
unsigned long ulFlags)
{
unsigned long ulFlags) {
unsigned long ulReadReg;
unsigned long ulWriteReg;
unsigned long ulStatReg;
@ -366,8 +346,7 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Check if count is multiple of word
//
if (ulCount % 4)
{
if (ulCount % 4) {
return -1;
}
@ -379,8 +358,7 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Check if output buffer pointer is 0
//
if (ulDout == 0)
{
if (ulDout == 0) {
ulOutIncr = 0;
ulTxDummy = 0xFFFFFFFF;
ulDout = &ulTxDummy;
@ -389,8 +367,7 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Check if input buffer pointer is 0
//
if (ulDin == 0)
{
if (ulDin == 0) {
ulInIncr = 0;
ulDin = &ulRxDummy;
}
@ -405,18 +382,15 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Enable CS based on Flag
//
if (ulFlags & SPI_CS_ENABLE)
{
if (ulFlags & SPI_CS_ENABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE;
}
while (ulCount)
{
while (ulCount) {
//
// Wait for space in output register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_TXS)) {
}
//
@ -427,8 +401,7 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Wait for data in input register/FIFO.
//
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS))
{
while (!(HWREG(ulStatReg) & MCSPI_CH0STAT_RXS)) {
}
//
@ -451,8 +424,7 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//
// Disable CS based on Flag
//
if (ulFlags & SPI_CS_DISABLE)
{
if (ulFlags & SPI_CS_DISABLE) {
HWREG(ulBase + MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE;
}
@ -471,24 +443,20 @@ static long SPITransfer32(unsigned long ulBase, unsigned long *ulDout,
//! \return Returns a SPI interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SPIIntNumberGet(unsigned long ulBase)
{
static long SPIIntNumberGet(unsigned long ulBase) {
unsigned long ulIdx;
//
// Loop through the table that maps SPI base addresses to interrupt
// numbers.
//
for (ulIdx = 0; ulIdx < (sizeof(g_ppulSPIIntMap) /
sizeof(g_ppulSPIIntMap[0]));
ulIdx++)
{
for (ulIdx = 0;
ulIdx < (sizeof(g_ppulSPIIntMap) / sizeof(g_ppulSPIIntMap[0]));
ulIdx++) {
//
// See if this base address matches.
//
if (g_ppulSPIIntMap[ulIdx][0] == ulBase)
{
if (g_ppulSPIIntMap[ulIdx][0] == ulBase) {
//
// Return the corresponding interrupt number.
//
@ -514,24 +482,20 @@ SPIIntNumberGet(unsigned long ulBase)
//! \return Returns a DMA interrupt mask bit, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SPIDmaMaskGet(unsigned long ulBase)
{
static long SPIDmaMaskGet(unsigned long ulBase) {
unsigned long ulIdx;
//
// Loop through the table that maps SPI base addresses to interrupt
// numbers.
//
for (ulIdx = 0; ulIdx < (sizeof(g_ulSPIDmaMaskMap) /
sizeof(g_ulSPIDmaMaskMap[0]));
ulIdx++)
{
for (ulIdx = 0;
ulIdx < (sizeof(g_ulSPIDmaMaskMap) / sizeof(g_ulSPIDmaMaskMap[0]));
ulIdx++) {
//
// See if this base address matches.
//
if (g_ulSPIDmaMaskMap[ulIdx][0] == ulBase)
{
if (g_ulSPIDmaMaskMap[ulIdx][0] == ulBase) {
//
// Return the corresponding interrupt number.
//
@ -557,8 +521,7 @@ SPIDmaMaskGet(unsigned long ulBase)
//!
//
//*****************************************************************************
void SPIEnable(unsigned long ulBase)
{
void SPIEnable(unsigned long ulBase) {
//
// Set Channel Enable Bit
//
@ -577,8 +540,7 @@ void SPIEnable(unsigned long ulBase)
//!
//
//*****************************************************************************
void SPIDisable(unsigned long ulBase)
{
void SPIDisable(unsigned long ulBase) {
//
// Reset Channel Enable Bit
//
@ -603,8 +565,7 @@ void SPIDisable(unsigned long ulBase)
//! \return None.
//
//*****************************************************************************
void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags)
{
void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags) {
//
// Enable DMA based on ulFlags
//
@ -629,8 +590,7 @@ void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags)
//! \return None.
//
//*****************************************************************************
void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags)
{
void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags) {
//
// Disable DMA based on ulFlags
//
@ -648,8 +608,7 @@ void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags)
//! \return None.
//
//*****************************************************************************
void SPIReset(unsigned long ulBase)
{
void SPIReset(unsigned long ulBase) {
//
// Assert soft reset (auto clear)
@ -659,8 +618,7 @@ void SPIReset(unsigned long ulBase)
//
// wait until reset is done
//
while (!(HWREG(ulBase + MCSPI_O_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE))
{
while (!(HWREG(ulBase + MCSPI_O_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE)) {
}
}
@ -733,8 +691,7 @@ void SPIReset(unsigned long ulBase)
//*****************************************************************************
void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
unsigned long ulBitRate, unsigned long ulMode,
unsigned long ulSubMode, unsigned long ulConfig)
{
unsigned long ulSubMode, unsigned long ulConfig) {
unsigned long ulRegData;
unsigned long ulDivider;
@ -747,8 +704,7 @@ void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
//
// Set Master mode with h/w chip select
//
ulRegData &= ~(MCSPI_MODULCTRL_MS |
MCSPI_MODULCTRL_SINGLE);
ulRegData &= ~(MCSPI_MODULCTRL_MS | MCSPI_MODULCTRL_SINGLE);
//
// Enable software control Chip Select, Init delay
@ -764,12 +720,9 @@ void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
//
// Set IS, DPE0, DPE1 based on master or slave mode
//
if (ulMode == SPI_MODE_MASTER)
{
if (ulMode == SPI_MODE_MASTER) {
ulRegData = 0x1 << 16;
}
else
{
} else {
ulRegData = 0x6 << 16;
}
@ -777,10 +730,8 @@ void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
// Mask the configurations and set clock divider granularity
// to 1 cycle
//
ulRegData = (ulRegData & ~(MCSPI_CH0CONF_WL_M |
MCSPI_CH0CONF_EPOL |
MCSPI_CH0CONF_POL |
MCSPI_CH0CONF_PHA |
ulRegData = (ulRegData & ~(MCSPI_CH0CONF_WL_M | MCSPI_CH0CONF_EPOL |
MCSPI_CH0CONF_POL | MCSPI_CH0CONF_PHA |
MCSPI_CH0CONF_TURBO) |
MCSPI_CH0CONF_CLKG);
@ -801,9 +752,7 @@ void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
// Set the protocol, CS polarity, word length
// and turbo mode
//
ulRegData = ((ulRegData |
ulSubMode) |
(ulConfig & 0x0008FFFF));
ulRegData = ((ulRegData | ulSubMode) | (ulConfig & 0x0008FFFF));
//
// Write back the CONF register
@ -824,8 +773,7 @@ void SPIConfigSetExpClk(unsigned long ulBase, unsigned long ulSPIClk,
//! \return Returns the number of elements read from the receive FIFO.
//
//*****************************************************************************
long SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
{
long SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) {
unsigned long ulRegVal;
//
@ -836,8 +784,7 @@ long SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//
// Check is data is available
//
if (ulRegVal & MCSPI_CH0STAT_RXS)
{
if (ulRegVal & MCSPI_CH0STAT_RXS) {
*pulData = HWREG(ulBase + MCSPI_O_RX0);
return (1);
}
@ -860,13 +807,11 @@ long SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//! \e unsigned long.
//
//*****************************************************************************
void SPIDataGet(unsigned long ulBase, unsigned long *pulData)
{
void SPIDataGet(unsigned long ulBase, unsigned long *pulData) {
//
// Wait for Rx data
//
while (!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS))
{
while (!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)) {
}
//
@ -888,8 +833,7 @@ void SPIDataGet(unsigned long ulBase, unsigned long *pulData)
//! \return Returns the number of elements written to the transmit FIFO.
//!
//*****************************************************************************
long SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
{
long SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) {
unsigned long ulRegVal;
//
@ -901,8 +845,7 @@ long SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
// Write value into Tx register/FIFO
// if space is available
//
if (ulRegVal & MCSPI_CH0STAT_TXS)
{
if (ulRegVal & MCSPI_CH0STAT_TXS) {
HWREG(ulBase + MCSPI_O_TX0) = ulData;
return (1);
}
@ -923,13 +866,11 @@ long SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
//! \return None
//!
//*****************************************************************************
void SPIDataPut(unsigned long ulBase, unsigned long ulData)
{
void SPIDataPut(unsigned long ulBase, unsigned long ulData) {
//
// Wait for space in FIFO
//
while (!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_TXS))
{
while (!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_TXS)) {
}
//
@ -955,8 +896,7 @@ void SPIDataPut(unsigned long ulBase, unsigned long ulData)
//! \return None.
//
//*****************************************************************************
void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags)
{
void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags) {
//
// Set FIFO enable bits.
//
@ -980,8 +920,7 @@ void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags)
//! \return None.
//
//*****************************************************************************
void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags)
{
void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags) {
//
// Reset FIFO Enable bits.
//
@ -1003,8 +942,7 @@ void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags)
//
//*****************************************************************************
void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel)
{
unsigned long ulRxLevel) {
unsigned long ulRegVal;
//
@ -1015,7 +953,8 @@ void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
//
// Mask and set new FIFO thresholds.
//
ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel - 1) << 8) | (ulTxLevel - 1)));
ulRegVal =
((ulRegVal & 0xFFFF0000) | (((ulRxLevel - 1) << 8) | (ulTxLevel - 1)));
//
// Set the transmit and receive FIFO thresholds.
@ -1038,8 +977,7 @@ void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
//
//*****************************************************************************
void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel)
{
unsigned long *pulRxLevel) {
unsigned long ulRegVal;
//
@ -1065,8 +1003,7 @@ void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
//! \return None.
//
//*****************************************************************************
void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
{
void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount) {
unsigned long ulRegVal;
//
@ -1077,8 +1014,8 @@ void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
//
// Mask and set the word count
//
HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF) |
(ulWordCount & 0xFFFF) << 16);
HWREG(ulBase + MCSPI_O_XFERLEVEL) =
((ulRegVal & 0x0000FFFF) | (ulWordCount & 0xFFFF) << 16);
}
//*****************************************************************************
@ -1100,8 +1037,7 @@ void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount)
//! \return None.
//
//*****************************************************************************
void SPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
void SPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) {
unsigned long ulInt;
//
@ -1137,8 +1073,7 @@ void SPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//! \return None.
//
//*****************************************************************************
void SPIIntUnregister(unsigned long ulBase)
{
void SPIIntUnregister(unsigned long ulBase) {
unsigned long ulInt;
//
@ -1181,15 +1116,13 @@ void SPIIntUnregister(unsigned long ulBase)
//! \return None.
//
//*****************************************************************************
void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) {
unsigned long ulDmaMsk;
//
// Enable DMA Tx Interrupt
//
if (ulIntFlags & SPI_INT_DMATX)
{
if (ulIntFlags & SPI_INT_DMATX) {
ulDmaMsk = SPIDmaMaskGet(ulBase);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
}
@ -1197,8 +1130,7 @@ void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Enable DMA Rx Interrupt
//
if (ulIntFlags & SPI_INT_DMARX)
{
if (ulIntFlags & SPI_INT_DMARX) {
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
}
@ -1226,15 +1158,13 @@ void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \return None.
//
//*****************************************************************************
void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) {
unsigned long ulDmaMsk;
//
// Disable DMA Tx Interrupt
//
if (ulIntFlags & SPI_INT_DMATX)
{
if (ulIntFlags & SPI_INT_DMATX) {
ulDmaMsk = SPIDmaMaskGet(ulBase);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
}
@ -1242,8 +1172,7 @@ void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Disable DMA Tx Interrupt
//
if (ulIntFlags & SPI_INT_DMARX)
{
if (ulIntFlags & SPI_INT_DMARX) {
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
}
@ -1270,9 +1199,7 @@ void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! values described in SPIIntEnable().
//
//*****************************************************************************
unsigned long
SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
{
unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked) {
unsigned long ulIntStat;
unsigned long ulIntFlag;
unsigned long ulDmaMsk;
@ -1282,8 +1209,7 @@ SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
//
ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F;
if (bMasked)
{
if (bMasked) {
ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE);
}
@ -1295,28 +1221,23 @@ SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
//
// Get the DMA interrupt status
//
if (bMasked)
{
if (bMasked) {
ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED);
}
else
{
} else {
ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
}
//
// Get SPI Tx DMA done status
//
if (ulIntStat & ulDmaMsk)
{
if (ulIntStat & ulDmaMsk) {
ulIntFlag |= SPI_INT_DMATX;
}
//
// Get SPI Rx DMA done status
//
if (ulIntStat & (ulDmaMsk >> 1))
{
if (ulIntStat & (ulDmaMsk >> 1)) {
ulIntFlag |= SPI_INT_DMARX;
}
@ -1343,15 +1264,13 @@ SPIIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \return None.
//
//*****************************************************************************
void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags) {
unsigned long ulDmaMsk;
//
// Disable DMA Tx Interrupt
//
if (ulIntFlags & SPI_INT_DMATX)
{
if (ulIntFlags & SPI_INT_DMATX) {
ulDmaMsk = SPIDmaMaskGet(ulBase);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
}
@ -1359,8 +1278,7 @@ void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//
// Disable DMA Tx Interrupt
//
if (ulIntFlags & SPI_INT_DMARX)
{
if (ulIntFlags & SPI_INT_DMARX) {
ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1);
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
}
@ -1384,8 +1302,7 @@ void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \return None.
//
//*****************************************************************************
void SPICSEnable(unsigned long ulBase)
{
void SPICSEnable(unsigned long ulBase) {
//
// Set Chip Select enable bit.
//
@ -1405,8 +1322,7 @@ void SPICSEnable(unsigned long ulBase)
//! \return None.
//
//*****************************************************************************
void SPICSDisable(unsigned long ulBase)
{
void SPICSDisable(unsigned long ulBase) {
//
// Reset Chip Select enable bit.
//
@ -1445,8 +1361,7 @@ void SPICSDisable(unsigned long ulBase)
//*****************************************************************************
long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
unsigned char *ucDin, unsigned long ulCount,
unsigned long ulFlags)
{
unsigned long ulFlags) {
unsigned long ulWordLength;
long lRet;
@ -1459,29 +1374,23 @@ long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
// Check for word length.
//
if (!((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) ||
(ulWordLength == SPI_WL_32)))
{
(ulWordLength == SPI_WL_32))) {
return -1;
}
if (ulWordLength == SPI_WL_8)
{
if (ulWordLength == SPI_WL_8) {
//
// Do byte transfer
//
lRet = SPITransfer8(ulBase, ucDout, ucDin, ulCount, ulFlags);
}
else if (ulWordLength == SPI_WL_16)
{
} else if (ulWordLength == SPI_WL_16) {
//
// Do half-word transfer
//
lRet = SPITransfer16(ulBase, (unsigned short *)ucDout,
(unsigned short *)ucDin, ulCount, ulFlags);
}
else
{
} else {
//
// Do word transfer
//

1129
cpu/cc3200/driverlib/uart.c
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File diff suppressed because it is too large Load Diff

135
cpu/cc3200/include/cc3200.h
View File

@ -32,11 +32,11 @@
#include "vendor/hw_types.h"
#include "vendor/rom_map.h"
// #include "driverlib/interrupt.h"
#include "driverlib/interrupt.h"
#include "driverlib/uart.h"
#include "driverlib/pin.h"
// #include "driverlib/gpio.h"
// #include "driverlib/spi.h"
#include "driverlib/gpio.h"
#include "driverlib/spi.h"
#include "driverlib/prcm.h"
#ifdef __cplusplus
@ -44,82 +44,81 @@ extern "C"
{
#endif
typedef volatile uint32_t cc3200_reg_t; /**< Least-significant 32 bits of the IEEE address */
typedef volatile uint32_t cc3200_reg_t; /**< Least-significant 32 bits of the IEEE address */
/* ************************************************************************** */
/* CMSIS DEFINITIONS FOR CC3200 */
/* ************************************************************************** */
/** @addtogroup CC3200_cmsis CMSIS Definitions */
/*@{*/
/* ************************************************************************** */
/* CMSIS DEFINITIONS FOR CC3200 */
/* ************************************************************************** */
/** @addtogroup CC3200_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************/
ResetHandler_IRQn = -15, /**< 1 Reset Handler */
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /**< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************/
ResetHandler_IRQn = -15, /**< 1 Reset Handler */
NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /**< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */
/****** CC3200 specific Interrupt Numbers ********************************/
GPIO_PORT_A0_IRQn = 0, /**< GPIO port A */
GPIO_PORT_A1_IRQn = 1, /**< GPIO port B */
GPIO_PORT_A2_IRQn = 2, /**< GPIO port C */
GPIO_PORT_A3_IRQn = 3, /**< GPIO port D */
UART0_IRQn = 5, /**< UART0 */
UART1_IRQn = 6, /**< UART1 */
I2C_IRQn = 8, /**< I2C */
ADC0_IRQn = 14, /**< ADC Sequence 0 */
ADC1_IRQn = 15, /**< ADC Sequence 1 */
ADC2_IRQn = 16, /**< ADC Sequence 2 */
ADC3_IRQn = 17, /**< ADC Sequence 3 */
WDT_IRQn = 18, /**< Watchdog Timer */
GPTIMER_0A_IRQn = 19, /**< GPTimer 0A */
GPTIMER_0B_IRQn = 20, /**< GPTimer 0B */
GPTIMER_1A_IRQn = 21, /**< GPTimer 1A */
GPTIMER_1B_IRQn = 22, /**< GPTimer 1B */
GPTIMER_2A_IRQn = 23, /**< GPTimer 2A */
GPTIMER_2B_IRQn = 24, /**< GPTimer 2B */
FLASH_CTRL_IRQn = 29, /**< Flash memory control */
GPTIMER_3A_IRQn = 35, /**< GPTimer 3A */
GPTIMER_3B_IRQn = 36, /**< GPTimer 3B */
UDMA_IRQn = 46, /**< uDMA software */
UDMA_ERR_IRQn = 47, /**< uDMA error */
SHA_IRQn = 148, /**< SHA */
AES_IRQn = 151, /**< AES */
DES_IRQn = 153, /**< DES */
MMCHS_IRQn = 159, /**< SDIO */
I2S_IRQn = 161, /**< McAPS */
CAMERA_IRQn = 163, /**< Camera */
NWPIC_IRQn = 171, /**< AES */
PRCM_IRQn = 172, /**< Power, Reset and Clock Module */
SSPI_IRQn = 175, /**< Shared SPI */
GSPI_IRQn = 176, /**< Generic SPI */
LSPI_IRQn = 177, /**< Link SPI */
IRQN_COUNT = (LSPI_IRQn + 1) /**< Number of peripheral IDs */
} IRQn_Type;
/****** CC3200 specific Interrupt Numbers ********************************/
GPIO_PORT_A0_IRQn = 0, /**< GPIO port A */
GPIO_PORT_A1_IRQn = 1, /**< GPIO port B */
GPIO_PORT_A2_IRQn = 2, /**< GPIO port C */
GPIO_PORT_A3_IRQn = 3, /**< GPIO port D */
UART0_IRQn = 5, /**< UART0 */
UART1_IRQn = 6, /**< UART1 */
I2C_IRQn = 8, /**< I2C */
ADC0_IRQn = 14, /**< ADC Sequence 0 */
ADC1_IRQn = 15, /**< ADC Sequence 1 */
ADC2_IRQn = 16, /**< ADC Sequence 2 */
ADC3_IRQn = 17, /**< ADC Sequence 3 */
WDT_IRQn = 18, /**< Watchdog Timer */
GPTIMER_0A_IRQn = 19, /**< GPTimer 0A */
GPTIMER_0B_IRQn = 20, /**< GPTimer 0B */
GPTIMER_1A_IRQn = 21, /**< GPTimer 1A */
GPTIMER_1B_IRQn = 22, /**< GPTimer 1B */
GPTIMER_2A_IRQn = 23, /**< GPTimer 2A */
GPTIMER_2B_IRQn = 24, /**< GPTimer 2B */
FLASH_CTRL_IRQn = 29, /**< Flash memory control */
GPTIMER_3A_IRQn = 35, /**< GPTimer 3A */
GPTIMER_3B_IRQn = 36, /**< GPTimer 3B */
UDMA_IRQn = 46, /**< uDMA software */
UDMA_ERR_IRQn = 47, /**< uDMA error */
SHA_IRQn = 148, /**< SHA */
AES_IRQn = 151, /**< AES */
DES_IRQn = 153, /**< DES */
MMCHS_IRQn = 159, /**< SDIO */
I2S_IRQn = 161, /**< McAPS */
CAMERA_IRQn = 163, /**< Camera */
NWPIC_IRQn = 171, /**< AES */
PRCM_IRQn = 172, /**< Power, Reset and Clock Module */
SSPI_IRQn = 175, /**< Shared SPI */
GSPI_IRQn = 176, /**< Generic SPI */
LSPI_IRQn = 177, /**< Link SPI */
IRQN_COUNT = (LSPI_IRQn + 1) /**< Number of peripheral IDs */
} IRQn_Type;
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001 /**< CC2538 core revision number ([15:8] revision number, [7:0] patch number) */
#define __MPU_PRESENT 0 /**< CC3200 does not provides an MPU */
#define __NVIC_PRIO_BITS 3 /**< CC3200 uses 3 Bits for Interrupt Priority Levels */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /**< CC3200 has not FPU */
#define __CM4_REV 0x0001 /**< CC2538 core revision number ([15:8] revision number, [7:0] patch number) */
#define __MPU_PRESENT 0 /**< CC3200 does not provides an MPU */
#define __NVIC_PRIO_BITS 3 /**< CC3200 uses 3 Bits for Interrupt Priority Levels */
#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0 /**< CC3200 has not FPU */
#define PERIPH_BASE 0x40000000U
#define SW_TIMERS_EXAUSTED 111
#define CC3200_VTOR_ALIGN 1024 /**< CC3200 Vector Table alignment */
#define CC3200_VTOR_ALIGN 1024 /**< CC3200 Vector Table alignment */
#ifdef __cplusplus
} /* end extern "C" */

48
cpu/cc3200/include/cc3200_gpio.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2019 Ludwig Maximilian Üniversitaet
* Copyright (C) 2019 Ludwig Maximilian Universität
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -14,7 +14,7 @@
* @file
* @brief Driver for the cc3200 GPIO controller
*
* Header file with register and macro declarations for the cc2538 GPIO module
* Header file with register and macro declarations for the cc3200 GPIO module
*
* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
*
@ -26,39 +26,55 @@
#include "cc3200.h"
#ifdef __cplusplus
extern "C" {
extern "C"
{
#endif
/**
/**
* @name Numeric representation of the four GPIO ports
* @{
*/
enum {
GPIO_PORT_A0 = 0,
GPIO_PORT_A1 = 1,
GPIO_PORT_A2 = 2,
GPIO_PORT_A3 = 3,
};
enum
{
PORT_A0 = 0,
PORT_A1 = 1,
PORT_A2 = 2,
PORT_A3 = 3,
};
/**
* @name Define a custom type for GPIO pins
* @{
*/
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
// typedef uint32_t gpio_t;
/** @} */
/**
* @brief Define a CPU specific GPIO pin generator macro
*/
#define GPIO_PIN(x, y) ((x << 6) | y)
#define GPIO_PIN(x, y) ((x << 6) | (y - 1))
#define GPIO_PINS_PER_PORT 8
#define LED_RED GPIO_PIN(1, 9)
#define LED_ORANGE GPIO_PIN(1, 10)
#define LED_GREEN GPIO_PIN(1, 11)
#define LED_RED GPIO_PIN(PORT_A1, 64) //9)
#define LED_ORANGE GPIO_PIN(PORT_A1, 1) //10)
#define LED_GREEN GPIO_PIN(PORT_A1, 2) //11)
typedef unsigned long cc3200_gpio_reg;
typedef struct cc3200_gpio_t
{
cc3200_gpio_reg data; // GPIO Data register
cc3200_gpio_reg RESERVER1[255]; // GPIO Reserved addresses
cc3200_gpio_reg dir; // GPIO Direction register
cc3200_gpio_reg is; // GPIO Interrupt Sense
cc3200_gpio_reg ibe; // GPIO Interrupt Both Edges
cc3200_gpio_reg iev; // GPIO Interrupt Event
cc3200_gpio_reg im; // GPIO Interrupt Mask
cc3200_gpio_reg ris; // GPIO Raw Interrupt Status
cc3200_gpio_reg mis; // GPIO Masked Interrupt Status
cc3200_gpio_reg icr; // GPIO Interrupt Clear
} cc3200_gpio_t;
#ifdef __cplusplus
} /* end extern "C" */

328
cpu/cc3200/include/cc3200_prcm.h
View File

@ -26,9 +26,9 @@
#include "cc3200.h"
#ifdef __cplusplus
extern "C" {
extern "C"
{
#endif
// Copied from TIs driverlib/prcm.h
@ -76,130 +76,320 @@ extern "C" {
// Values that can be passed to PRCMPeripheralEnable() and
// PRCMPeripheralDisable()
//*****************************************************************************
#define PRCM_RUN_MODE_CLK 0x00000001
#define PRCM_SLP_MODE_CLK 0x00000100
#define PRCM_DSLP_MODE_CLK 0x00010000
#define PRCM_RUN_MODE_CLK 0x00000001
#define PRCM_SLP_MODE_CLK 0x00000100
#define PRCM_DSLP_MODE_CLK 0x00010000
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulSramColSel.
//*****************************************************************************
#define PRCM_SRAM_COL_1 0x00000001
#define PRCM_SRAM_COL_2 0x00000002
#define PRCM_SRAM_COL_3 0x00000004
#define PRCM_SRAM_COL_4 0x00000008
#define PRCM_SRAM_COL_1 0x00000001
#define PRCM_SRAM_COL_2 0x00000002
#define PRCM_SRAM_COL_3 0x00000004
#define PRCM_SRAM_COL_4 0x00000008
//*****************************************************************************
// Values that can be passed to PRCMSRAMRetentionEnable() and
// PRCMSRAMRetentionDisable() as ulModeFlags.
//*****************************************************************************
#define PRCM_SRAM_DSLP_RET 0x00000001
#define PRCM_SRAM_LPDS_RET 0x00000002
#define PRCM_SRAM_DSLP_RET 0x00000001
#define PRCM_SRAM_LPDS_RET 0x00000002
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
//*****************************************************************************
#define PRCM_LPDS_HOST_IRQ 0x00000080
#define PRCM_LPDS_GPIO 0x00000010
#define PRCM_LPDS_TIMER 0x00000001
#define PRCM_LPDS_HOST_IRQ 0x00000080
#define PRCM_LPDS_GPIO 0x00000010
#define PRCM_LPDS_TIMER 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
//*****************************************************************************
#define PRCM_LPDS_LOW_LEVEL 0x00000002
#define PRCM_LPDS_HIGH_LEVEL 0x00000000
#define PRCM_LPDS_FALL_EDGE 0x00000001
#define PRCM_LPDS_RISE_EDGE 0x00000003
#define PRCM_LPDS_LOW_LEVEL 0x00000002
#define PRCM_LPDS_HIGH_LEVEL 0x00000000
#define PRCM_LPDS_FALL_EDGE 0x00000001
#define PRCM_LPDS_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_LPDS_GPIO2 0x00000000
#define PRCM_LPDS_GPIO4 0x00000001
#define PRCM_LPDS_GPIO13 0x00000002
#define PRCM_LPDS_GPIO17 0x00000003
#define PRCM_LPDS_GPIO11 0x00000004
#define PRCM_LPDS_GPIO24 0x00000005
#define PRCM_LPDS_GPIO26 0x00000006
#define PRCM_LPDS_GPIO2 0x00000000
#define PRCM_LPDS_GPIO4 0x00000001
#define PRCM_LPDS_GPIO13 0x00000002
#define PRCM_LPDS_GPIO17 0x00000003
#define PRCM_LPDS_GPIO11 0x00000004
#define PRCM_LPDS_GPIO24 0x00000005
#define PRCM_LPDS_GPIO26 0x00000006
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable().
//*****************************************************************************
#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
//*****************************************************************************
#define PRCM_HIB_LOW_LEVEL 0x00000000
#define PRCM_HIB_HIGH_LEVEL 0x00000001
#define PRCM_HIB_FALL_EDGE 0x00000002
#define PRCM_HIB_RISE_EDGE 0x00000003
#define PRCM_HIB_LOW_LEVEL 0x00000000
#define PRCM_HIB_HIGH_LEVEL 0x00000001
#define PRCM_HIB_FALL_EDGE 0x00000002
#define PRCM_HIB_RISE_EDGE 0x00000003
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
//*****************************************************************************
#define PRCM_HIB_GPIO2 0x00010000
#define PRCM_HIB_GPIO4 0x00020000
#define PRCM_HIB_GPIO13 0x00040000
#define PRCM_HIB_GPIO17 0x00080000
#define PRCM_HIB_GPIO11 0x00100000
#define PRCM_HIB_GPIO24 0x00200000
#define PRCM_HIB_GPIO26 0x00400000
#define PRCM_HIB_GPIO2 0x00010000
#define PRCM_HIB_GPIO4 0x00020000
#define PRCM_HIB_GPIO13 0x00040000
#define PRCM_HIB_GPIO17 0x00080000
#define PRCM_HIB_GPIO11 0x00100000
#define PRCM_HIB_GPIO24 0x00200000
#define PRCM_HIB_GPIO26 0x00400000
//*****************************************************************************
// Values that will be returned from PRCMSysResetCauseGet().
//*****************************************************************************
#define PRCM_POWER_ON 0x00000000
#define PRCM_LPDS_EXIT 0x00000001
#define PRCM_CORE_RESET 0x00000003
#define PRCM_MCU_RESET 0x00000004
#define PRCM_WDT_RESET 0x00000005
#define PRCM_SOC_RESET 0x00000006
#define PRCM_HIB_EXIT 0x00000007
#define PRCM_POWER_ON 0x00000000
#define PRCM_LPDS_EXIT 0x00000001
#define PRCM_CORE_RESET 0x00000003
#define PRCM_MCU_RESET 0x00000004
#define PRCM_WDT_RESET 0x00000005
#define PRCM_SOC_RESET 0x00000006
#define PRCM_HIB_EXIT 0x00000007
//*****************************************************************************
// Values that can be passed to PRCMHibernateWakeupCauseGet().
//*****************************************************************************
#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
//*****************************************************************************
// Values that can be passed to PRCMSEnableInterrupt
//*****************************************************************************
#define PRCM_INT_SLOW_CLK_CTR 0x00004000
#define PRCM_INT_SLOW_CLK_CTR 0x00004000
//*****************************************************************************
// Values that can be passed to PRCMPeripheralClkEnable(),
// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
//*****************************************************************************
#define PRCM_CAMERA 0x00000000
#define PRCM_I2S 0x00000001
#define PRCM_SDHOST 0x00000002
#define PRCM_GSPI 0x00000003
#define PRCM_LSPI 0x00000004
#define PRCM_UDMA 0x00000005
#define PRCM_GPIOA0 0x00000006
#define PRCM_GPIOA1 0x00000007
#define PRCM_GPIOA2 0x00000008
#define PRCM_GPIOA3 0x00000009
#define PRCM_GPIOA4 0x0000000A
#define PRCM_WDT 0x0000000B
#define PRCM_UARTA0 0x0000000C
#define PRCM_UARTA1 0x0000000D
#define PRCM_TIMERA0 0x0000000E
#define PRCM_TIMERA1 0x0000000F
#define PRCM_TIMERA2 0x00000010
#define PRCM_TIMERA3 0x00000011
#define PRCM_DTHE 0x00000012
#define PRCM_SSPI 0x00000013
#define PRCM_I2CA0 0x00000014
#define PRCM_CAMERA 0x00000000
#define PRCM_I2S 0x00000001
#define PRCM_SDHOST 0x00000002
#define PRCM_GSPI 0x00000003
#define PRCM_LSPI 0x00000004
#define PRCM_UDMA 0x00000005
#define PRCM_GPIOA0 0x00000006
#define PRCM_GPIOA1 0x00000007
#define PRCM_GPIOA2 0x00000008
#define PRCM_GPIOA3 0x00000009
#define PRCM_GPIOA4 0x0000000A
#define PRCM_WDT 0x0000000B
#define PRCM_UARTA0 0x0000000C
#define PRCM_UARTA1 0x0000000D
#define PRCM_TIMERA0 0x0000000E
#define PRCM_TIMERA1 0x0000000F
#define PRCM_TIMERA2 0x00000010
#define PRCM_TIMERA3 0x00000011
#define PRCM_DTHE 0x00000012
#define PRCM_SSPI 0x00000013
#define PRCM_I2CA0 0x00000014
// Note : PRCM_ADC is a dummy define for pinmux utility code generation
// PRCM_ADC should never be used in any user code.
#define PRCM_ADC 0x000000FF
#define PRCM_ADC 0x000000FF
#define PRCM_SOFT_RESET 0x00000001
#define PRCM_ENABLE_STATUS 0x00000002
typedef struct cc3200_periph_regs_t
{
cc3200_reg_t clk_gating;
cc3200_reg_t soft_reset;
} cc3200_periph_regs_t;
typedef struct cc3200_arcm_t
{
cc3200_reg_t CAM_CLK_GEN;
cc3200_periph_regs_t CAM;
cc3200_reg_t RESERVED1[2];
cc3200_periph_regs_t MCASP;
cc3200_reg_t RESERVED2[1];
cc3200_reg_t MMCHS_CLK_GEN;
cc3200_periph_regs_t MMCHS;
cc3200_reg_t MCSPI_A1_CLK_GEN;
cc3200_periph_regs_t MCSPI_A1;
cc3200_reg_t MCSPI_A2_CLK_GEN;
cc3200_reg_t RESERVED3[1];
cc3200_periph_regs_t MCSPI_A2;
cc3200_periph_regs_t UDMA_A;
cc3200_periph_regs_t GPIO_A;
cc3200_periph_regs_t GPIO_B;
cc3200_periph_regs_t GPIO_C;
cc3200_periph_regs_t GPIO_D;
cc3200_periph_regs_t GPIO_E;
cc3200_periph_regs_t WDOG_A;
cc3200_periph_regs_t UART_A0;
cc3200_periph_regs_t UART_A1;
cc3200_periph_regs_t GPT_A0;
cc3200_periph_regs_t GPT_A1;
cc3200_periph_regs_t GPT_A2;
cc3200_periph_regs_t GPT_A3;
cc3200_reg_t MCASP_FRAC_CLK_CONFIG0;
cc3200_reg_t MCASP_FRAC_CLK_CONFIG1;
cc3200_periph_regs_t CRYPTO;
cc3200_reg_t RESERVED4[2];
cc3200_periph_regs_t MCSPI_S0;
cc3200_reg_t MCSPI_S0_CLKDIV_CFG;
cc3200_reg_t RESERVED5[1];
cc3200_periph_regs_t I2C;
} cc3200_arcm_t;
#define ARCM ((cc3200_arcm_t *)0x44025000) /**< One and only instance of the System Control module */
typedef struct cc3200_gprcm_t
{
cc3200_reg_t APPS_SOFT_RESET;
cc3200_reg_t APPS_LPDS_WAKEUP_CFG;
cc3200_reg_t APPS_LPDS_WAKEUP_SRC;
cc3200_reg_t APPS_RESET_CAUSE;
cc3200_reg_t APPS_LPDS_WAKETIME_OPP_CFG;
cc3200_reg_t RESERVER1[1];
cc3200_reg_t APPS_SRAM_DSLP_CFG;
cc3200_reg_t APPS_SRAM_LPDS_CFG;
cc3200_reg_t APPS_LPDS_WAKETIME_WAKE_CFG;
cc3200_reg_t RESERVER2[55];
cc3200_reg_t TOP_DIE_ENABLE;
cc3200_reg_t TOP_DIE_ENABLE_PARAMETERS;
cc3200_reg_t MCU_GLOBAL_SOFT_RESET;
cc3200_reg_t ADC_CLK_CONFIG;
cc3200_reg_t APPS_GPIO_WAKE_CONF;
cc3200_reg_t EN_NWP_BOOT_WO_DEVINIT;
cc3200_reg_t MEM_HCLK_DIV_CFG;
cc3200_reg_t MEM_SYSCLK_DIV_CFG;
cc3200_reg_t APLLMCS_LOCK_TIME_CONF;
cc3200_reg_t RESERVER3[183];
cc3200_reg_t NWP_SOFT_RESET;
cc3200_reg_t NWP_LPDS_WAKEUP_CFG;
cc3200_reg_t NWP_LPDS_WAKEUP_SRC;
cc3200_reg_t NWP_RESET_CAUSE;
cc3200_reg_t NWP_LPDS_WAKETIME_OPP_CFG;
cc3200_reg_t RESERVER31[1];
cc3200_reg_t NWP_SRAM_DSLP_CFG;
cc3200_reg_t NWP_SRAM_LPDS_CFG;
cc3200_reg_t NWP_LPDS_WAKETIME_WAKE_CFG;
cc3200_reg_t NWP_AUTONMS_SPI_MASTER_SEL;
cc3200_reg_t NWP_AUTONMS_SPI_IDLE_REQ;
cc3200_reg_t WLAN_TO_NWP_WAKE_REQUEST;
cc3200_reg_t NWP_TO_WLAN_WAKE_REQUEST;
cc3200_reg_t NWP_GPIO_WAKE_CONF;
cc3200_reg_t GPRCM_EFUSE_READ_REG12;
cc3200_reg_t RESERVER32[3];
cc3200_reg_t GPRCM_DIEID_READ_REG5;
cc3200_reg_t GPRCM_DIEID_READ_REG6;
cc3200_reg_t RESERVER4[236];
cc3200_reg_t REF_FSM_CFG0;
cc3200_reg_t REF_FSM_CFG1;
cc3200_reg_t APLLMCS_WLAN_CONFIG0_40;
cc3200_reg_t APLLMCS_WLAN_CONFIG1_40;
cc3200_reg_t APLLMCS_WLAN_CONFIG0_26;
cc3200_reg_t APLLMCS_WLAN_CONFIG1_26;
cc3200_reg_t APLLMCS_WLAN_OVERRIDES;
cc3200_reg_t APLLMCS_MCU_RUN_CONFIG0_38P4;
cc3200_reg_t APLLMCS_MCU_RUN_CONFIG1_38P4;
cc3200_reg_t APLLMCS_MCU_RUN_CONFIG0_26;
cc3200_reg_t APLLMCS_MCU_RUN_CONFIG1_26;
cc3200_reg_t SPARE_RW0;
cc3200_reg_t SPARE_RW1;
cc3200_reg_t APLLMCS_MCU_OVERRIDES;
cc3200_reg_t SYSCLK_SWITCH_STATUS;
cc3200_reg_t REF_LDO_CONTROLS;
cc3200_reg_t REF_RTRIM_CONTROL;
cc3200_reg_t REF_SLICER_CONTROLS0;
cc3200_reg_t REF_SLICER_CONTROLS1;
cc3200_reg_t REF_ANA_BGAP_CONTROLS0;
cc3200_reg_t REF_ANA_BGAP_CONTROLS1;
cc3200_reg_t REF_ANA_SPARE_CONTROLS0;
cc3200_reg_t REF_ANA_SPARE_CONTROLS1;
cc3200_reg_t MEMSS_PSCON_OVERRIDES0;
cc3200_reg_t MEMSS_PSCON_OVERRIDES1;
cc3200_reg_t PLL_REF_LOCK_OVERRIDES;
cc3200_reg_t MCU_PSCON_DEBUG;
cc3200_reg_t MEMSS_PWR_PS;
cc3200_reg_t REF_FSM_DEBUG;
cc3200_reg_t MEM_SYS_OPP_REQ_OVERRIDE;
cc3200_reg_t MEM_TESTCTRL_PD_OPP_CONFIG;
cc3200_reg_t MEM_WL_FAST_CLK_REQ_OVERRIDES;
cc3200_reg_t MEM_MCU_PD_MODE_REQ_OVERRIDES;
cc3200_reg_t MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES;
cc3200_reg_t MEM_WLAN_APLLMCS_OVERRIDES;
cc3200_reg_t MEM_REF_FSM_CFG2;
cc3200_reg_t RESERVER5[224];
cc3200_reg_t TESTCTRL_POWER_CTRL;
cc3200_reg_t SSDIO_POWER_CTRL;
cc3200_reg_t MCSPI_N1_POWER_CTRL;
cc3200_reg_t WELP_POWER_CTRL;
cc3200_reg_t WL_SDIO_POWER_CTRL;
cc3200_reg_t WLAN_SRAM_ACTIVE_PWR_CFG;
cc3200_reg_t RESERVER6[1];
cc3200_reg_t WLAN_SRAM_SLEEP_PWR_CFG;
cc3200_reg_t APPS_SECURE_INIT_DONE;
cc3200_reg_t APPS_DEV_MODE_INIT_DONE;
cc3200_reg_t EN_APPS_REBOOT;
cc3200_reg_t MEM_APPS_PERIPH_PRESENT;
cc3200_reg_t MEM_NWP_PERIPH_PRESENT;
cc3200_reg_t MEM_SHARED_PERIPH_PRESENT;
cc3200_reg_t NWP_PWR_STATE;
cc3200_reg_t APPS_PWR_STATE;
cc3200_reg_t MCU_PWR_STATE;
cc3200_reg_t WTOP_PM_PS;
cc3200_reg_t WTOP_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t WELP_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t WL_SDIO_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t SSDIO_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t MCSPI_N1_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t TESTCTRL_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t MCU_PD_RESETZ_OVERRIDE_REG;
cc3200_reg_t RESERVER7[1];
cc3200_reg_t GPRCM_EFUSE_READ_REG0;
cc3200_reg_t GPRCM_EFUSE_READ_REG1;
cc3200_reg_t GPRCM_EFUSE_READ_REG2;
cc3200_reg_t GPRCM_EFUSE_READ_REG3;
cc3200_reg_t WTOP_MEM_RET_CFG;
cc3200_reg_t COEX_CLK_SWALLOW_CFG0;
cc3200_reg_t COEX_CLK_SWALLOW_CFG1;
cc3200_reg_t COEX_CLK_SWALLOW_CFG2;
cc3200_reg_t COEX_CLK_SWALLOW_ENABLE;
cc3200_reg_t DCDC_CLK_GEN_CONFIG;
cc3200_reg_t GPRCM_EFUSE_READ_REG4;
cc3200_reg_t GPRCM_EFUSE_READ_REG5;
cc3200_reg_t GPRCM_EFUSE_READ_REG6;
cc3200_reg_t GPRCM_EFUSE_READ_REG7;
cc3200_reg_t GPRCM_EFUSE_READ_REG8;
cc3200_reg_t GPRCM_EFUSE_READ_REG9;
cc3200_reg_t GPRCM_EFUSE_READ_REG10;
cc3200_reg_t GPRCM_EFUSE_READ_REG11;
cc3200_reg_t GPRCM_DIEID_READ_REG0;
cc3200_reg_t GPRCM_DIEID_READ_REG1;
cc3200_reg_t GPRCM_DIEID_READ_REG2;
cc3200_reg_t GPRCM_DIEID_READ_REG3;
cc3200_reg_t GPRCM_DIEID_READ_REG4;
cc3200_reg_t APPS_SS_OVERRIDES;
cc3200_reg_t NWP_SS_OVERRIDES;
cc3200_reg_t SHARED_SS_OVERRIDES;
cc3200_reg_t IDMEM_CORE_RST_OVERRIDES;
cc3200_reg_t TOP_DIE_FSM_OVERRIDES;
cc3200_reg_t MCU_PSCON_OVERRIDES;
cc3200_reg_t WTOP_PSCON_OVERRIDES;
cc3200_reg_t WELP_PSCON_OVERRIDES;
cc3200_reg_t WL_SDIO_PSCON_OVERRIDES;
cc3200_reg_t MCSPI_PSCON_OVERRIDES;
cc3200_reg_t SSDIO_PSCON_OVERRIDES;
} cc3200_gprcm_t;
#define GPRCM_BASE 0x4402D000
#define GPRCM ((cc3200_gprcm_t *)GPRCM_BASE) /**< One and only instance of the G Power Control Module */
#ifdef __cplusplus
} /* end extern "C" */

84
cpu/cc3200/include/cc3200_spi.h
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@ -1,10 +1,34 @@
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
//*****************************************************************************
#define SPI_SW_CTRL_CS 0x01000000
#define SPI_HW_CTRL_CS 0x00000000
#define SPI_3PIN_MODE 0x02000000
#define SPI_4PIN_MODE 0x00000000
#define SPI_TURBO_ON 0x00080000
#define SPI_TURBO_OFF 0x00000000
#define SPI_CS_ACTIVEHIGH 0x00000000
#define SPI_CS_ACTIVELOW 0x00000040
#define SPI_WL_8 0x00000380
#define SPI_WL_16 0x00000780
#define SPI_WL_32 0x00000F80
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
//*****************************************************************************
#define SPI_SUB_MODE_0 0x00000000
#define SPI_SUB_MODE_1 0x00000001
#define SPI_SUB_MODE_2 0x00000002
#define SPI_SUB_MODE_3 0x00000003
/**
* @brief Override SPI clock speed values
* @{
*/
#define HAVE_SPI_CLK_T 1
typedef enum {
typedef enum
{
SPI_CLK_100KHZ = 100000, /**< drive the SPI bus with 100KHz */
SPI_CLK_400KHZ = 400000, /**< drive the SPI bus with 400KHz */
SPI_CLK_1MHZ = 1000000, /**< drive the SPI bus with 1MHz */
@ -21,7 +45,8 @@ typedef enum {
* @{
*/
#define HAVE_SPI_MODE_T 1
typedef enum {
typedef enum
{
SPI_MODE_0 = 0x00000000, /**< CPOL=0, CPHA=0 */
SPI_MODE_1 = 0x00000001, /**< CPOL=0, CPHA=1 */
SPI_MODE_2 = 0x00000002, /**< CPOL=1, CPHA=0 */
@ -29,52 +54,59 @@ typedef enum {
} spi_mode_t;
/** @} */
typedef struct {
unsigned long mosi; /**< pin used for MOSI */
unsigned long miso; /**< pin used for MISO */
unsigned long sck; /**< pin used for SCK */
unsigned long cs; /**< pin used for CS */
typedef struct
{
unsigned long mosi; /**< pin used for MOSI */
unsigned long miso; /**< pin used for MISO */
unsigned long sck; /**< pin used for SCK */
unsigned long cs; /**< pin used for CS */
} spi_pins_t;
/**
* @brief SPI configuration data structure
* @{
*/
typedef struct {
typedef struct
{
unsigned long base_addr; /**< bus address */
unsigned long gpio_port; /**< GPIO port */
spi_pins_t pins;
unsigned long config; /**< SPI config */
} spi_conf_t;
/** @} */
typedef struct cc3200_spi_hwinfo {
unsigned long u1;
unsigned long u2;
unsigned long u3;
unsigned long u4;
typedef struct cc3200_spi_hwinfo
{
unsigned long u1;
unsigned long u2;
unsigned long u3;
unsigned long u4;
} cc3200_spi_hwinfo;
typedef struct cc3200_spi_sys_rev {
unsigned long u0;
unsigned long u1;
unsigned long u2;
typedef struct cc3200_spi_sys_rev
{
unsigned long u0;
unsigned long u1;
unsigned long u2;
} cc3200_spi_sys_rev;
typedef struct cc3200_spi_t {
unsigned long rev; // hardware revision
cc3200_spi_hwinfo hwinfo; // hardware info (HDL generics)
char gap_0[240]; // Sysconfig
cc3200_spi_sys_rev sys_rev; // System revision number
typedef struct cc3200_spi_t
{
unsigned long rev; // hardware revision
cc3200_spi_hwinfo hwinfo; // hardware info (HDL generics)
char gap_0[240]; // Sysconfig
cc3200_spi_sys_rev sys_rev; // System revision number
unsigned long sys_conf; // System config
unsigned long sys_status; // Sysstatus
unsigned long irq_status; // IRQStatus
unsigned long irq_enable; // IRQEnable
unsigned long wakeup_enable; // Wakeupenable
unsigned long sys_test; // system test mode
unsigned long module_ctl; // MODULE CTL
unsigned long ch0_conf_ctl; // CH0CONF CTL
unsigned long stat; // CH0 Status register
unsigned long ctrl; // CH0 Control register
unsigned long module_ctrl; // MODULE CTL
unsigned long ch0_conf; // CH0CONF CTL
unsigned long ch0_stat; // CH0 Status register
unsigned long ch0_ctrl; // CH0 Control register
unsigned long tx0; // single spi transmit word
unsigned long rx0; // single spi receive word
} cc3200_spi_t;

193
cpu/cc3200/include/cc3200_uart.h Normal file
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@ -0,0 +1,193 @@
/*
* Copyright (C) 2014 Loci Controls Inc.
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup cpu_cc3200_uart CC3200 UART
* @ingroup cpu_cc3200_regs
* @{
*
* @file
* @brief CC3200 UART interface
*
* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
*/
#ifndef CC3200_UART_H
#define CC3200_UART_H
#include "cc3200.h"
#ifdef __cplusplus
extern "C"
{
#endif
typedef unsigned long cc3200_uart_reg;
typedef struct cc3200_uart_t
{
cc3200_uart_reg dr; /**< UART Data Register */
union {
cc3200_uart_reg rsr; /**< UART receive status and error clear */
cc3200_uart_reg ecr; /**< UART receive status and error clear */
} cc3200_uart_dr;
cc3200_reg_t RESERVED1[4];
union {
cc3200_uart_reg raw; // flag
struct
{
cc3200_uart_reg CTS : 1; /**< Clear to send (UART1 only) */
cc3200_uart_reg DSR : 1; /**< Data Set Ready */
cc3200_uart_reg DCD : 1; /**< Data Carrier Detect */
cc3200_uart_reg BUSY : 1; /**< UART busy */
cc3200_uart_reg RXFE : 1; /**< UART receive FIFO empty */
cc3200_uart_reg TXFF : 1; /**< UART transmit FIFO full */
cc3200_uart_reg RXFF : 1; /**< UART receive FIFO full */
cc3200_uart_reg TXFE : 1; /**< UART transmit FIFO empty */
cc3200_uart_reg RI : 1; /**< UART ring indicator */
cc3200_uart_reg RESERVED1 : 23; /**< Reserved bits */
} bits;
} flags;
cc3200_uart_reg RESERVED2; /**< Reserved byte */
cc3200_uart_reg ILPR; /**< UART IrDA Low-Power Register */
cc3200_uart_reg IBRD; /**< UART Integer Baud-Rate Divisor */
cc3200_uart_reg FBRD; /**< UART Fractional Baud-Rate Divisor */
/**
* @brief Line control register
*/
union {
cc3200_uart_reg raw; /**< UART Line Control Register */
struct
{
cc3200_uart_reg BRK : 1; /**< UART send break */
cc3200_uart_reg PEN : 1; /**< UART parity enable */
cc3200_uart_reg EPS : 1; /**< UART even parity select */
cc3200_uart_reg STP2 : 1; /**< UART two stop bits select */
cc3200_uart_reg FEN : 1; /**< UART enable FIFOs */
cc3200_uart_reg WLEN : 2; /**< UART word length */
cc3200_uart_reg SPS : 1; /**< UART stick parity select */
cc3200_uart_reg RESERVED : 24; /**< Reserved bits */
} bits;
} LCRH;
/**
* @brief Control register
*/
union {
cc3200_uart_reg raw; /**< UART Control */
struct
{
cc3200_uart_reg UARTEN : 1; /**< UART enable */
cc3200_uart_reg SIREN : 1; /**< UART SIR enable */
cc3200_uart_reg SIRLP : 1; /**< UART SIR low-power mode */
cc3200_uart_reg RESERVED11 : 1; /**< Reserved bits */
cc3200_uart_reg EOT : 1; /**< End of transmission */
cc3200_uart_reg HSE : 1; /**< High-speed enable */
cc3200_uart_reg LIN : 1; /**< LIN mode enable */
cc3200_uart_reg LBE : 1; /**< UART loop back enable */
cc3200_uart_reg TXE : 1; /**< UART transmit enable */
cc3200_uart_reg RXE : 1; /**< UART receive enable */
cc3200_uart_reg RESERVED12 : 4; /**< Reserved bits */
cc3200_uart_reg RTSEN : 1; /**< U1RTS Hardware flow control enable */
cc3200_uart_reg CTSEN : 1; /**< U1CTS Hardware flow control enable */
cc3200_uart_reg RESERVED13 : 16; /**< Reserved bits */
} bits;
} CTL;
/**
* @brief Interrupt FIFO level select register
*/
union {
cc3200_uart_reg raw; /**< UART interrupt FIFO Level Select */
struct
{
cc3200_uart_reg TXIFLSEL : 3; /**< UART transmit interrupt FIFO level select */
cc3200_uart_reg RXIFLSEL : 3; /**< UART receive interrupt FIFO level select */
cc3200_uart_reg RESERVED : 26; /**< Reserved bits */
} bits;
} IFLS;
/**
* @brief Interrupt mask register
*/
union {
cc3200_uart_reg raw; /**< UART Interrupt Mask */
struct
{
cc3200_uart_reg RESERVED3 : 4; /**< Reserved bits */
cc3200_uart_reg RXIM : 1; /**< UART receive interrupt mask */
cc3200_uart_reg TXIM : 1; /**< UART transmit interrupt mask */
cc3200_uart_reg RTIM : 1; /**< UART receive time-out interrupt mask */
cc3200_uart_reg FEIM : 1; /**< UART framing error interrupt mask */
cc3200_uart_reg PEIM : 1; /**< UART parity error interrupt mask */
cc3200_uart_reg BEIM : 1; /**< UART break error interrupt mask */
cc3200_uart_reg OEIM : 1; /**< UART overrun error interrupt mask */
cc3200_uart_reg RESERVED2 : 1; /**< Reserved bits */
cc3200_uart_reg NINEBITM : 1; /**< 9-bit mode interrupt mask */
cc3200_uart_reg LMSBIM : 1; /**< LIN mode sync break interrupt mask */
cc3200_uart_reg LME1IM : 1; /**< LIN mode edge 1 interrupt mask */
cc3200_uart_reg LME5IM : 1; /**< LIN mode edge 5 interrupt mask */
cc3200_uart_reg RESERVED1 : 16; /**< Reserved bits */
} bits;
} IM;
cc3200_uart_reg RIS; /**< UART Raw Interrupt Status */
/**
* @brief Masked interrupt status register
*/
union {
cc3200_uart_reg raw; /**< UART Masked Interrupt Status */
struct
{
cc3200_uart_reg RESERVED8 : 4; /**< Reserved bits */
cc3200_uart_reg RXMIS : 1; /**< UART receive masked interrupt status */
cc3200_uart_reg TXMIS : 1; /**< UART transmit masked interrupt status */
cc3200_uart_reg RTMIS : 1; /**< UART receive time-out masked interrupt status */
cc3200_uart_reg FEMIS : 1; /**< UART framing error masked interrupt status */
cc3200_uart_reg PEMIS : 1; /**< UART parity error masked interrupt status */
cc3200_uart_reg BEMIS : 1; /**< UART break error masked interrupt status */
cc3200_uart_reg OEMIS : 1; /**< UART overrun error masked interrupt status */
cc3200_uart_reg RESERVED9 : 1; /**< Reserved bits */
cc3200_uart_reg NINEBITMIS : 1; /**< 9-bit mode masked interrupt status */
cc3200_uart_reg LMSBMIS : 1; /**< LIN mode sync break masked interrupt status */
cc3200_uart_reg LME1MIS : 1; /**< LIN mode edge 1 masked interrupt status */
cc3200_uart_reg LME5MIS : 1; /**< LIN mode edge 5 masked interrupt status */
cc3200_uart_reg RESERVED10 : 16; /**< Reserved bits */
} bits;
} MIS;
cc3200_uart_reg ICR; /**< UART Interrupt Clear Register */
cc3200_uart_reg DMACTL; /**< UART DMA Control */
cc3200_uart_reg RESERVED3[17]; /**< Reserved addresses */
cc3200_uart_reg LCTL; /**< UART LIN Control */
cc3200_uart_reg LSS; /**< UART LIN Snap Shot */
cc3200_uart_reg LTIM; /**< UART LIN Timer */
cc3200_uart_reg RESERVED4[2]; /**< Reserved addresses */
cc3200_uart_reg NINEBITADDR; /**< UART 9-bit self Address */
cc3200_uart_reg NINEBITAMASK; /**< UART 9-bit self Address Mask */
cc3200_uart_reg RESERVED5[965]; /**< Reserved addresses */
cc3200_uart_reg PP; /**< UART Peripheral Properties */
cc3200_uart_reg RESERVED6; /**< Reserved addresses */
cc3200_uart_reg CC; /**< UART Clock Configuration */
cc3200_uart_reg RESERVED7[13]; /**< Reserved addresses */
} cc3200_uart_t;
#define UART0 (cc3200_uart_t *)(0x4000C000) /**< UART0 Instance */
#define UART1 (cc3200_uart_t *)(0x4000D000) /**< UART1 Instance */
#ifdef __cplusplus
} /* end extern "C" */
#endif
#endif /* CC3200_UART_H */
/** @} */

12
cpu/cc3200/include/cpu_conf.h
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@ -13,20 +13,24 @@
#include "cc3200.h"
#include "cc3200_spi.h"
#include "cc3200_gpio.h"
#include "cc3200_uart.h"
#include "cc3200_prcm.h"
#ifdef __cplusplus
extern "C"
{
#endif
extern void init_periph_clk(cc3200_periph_regs_t *reg);
/**
* @brief ARM Cortex-M specific CPU configuration
* @{
*/
#define CPU_DEFAULT_IRQ_PRIO (1U) /**< The default priority is 1 for every interrupt, 0 is the highest possible priority. */
#define CPU_IRQ_NUMOF IRQN_COUNT
#define CPU_FLASH_BASE FLASH_BASE /**< number of interrupt sources */
/** @} */
#define CPU_DEFAULT_IRQ_PRIO (1U) /**< The default priority is 1 for every interrupt, 0 is the highest possible priority. */
#define CPU_IRQ_NUMOF IRQN_COUNT /**< number of interrupt sources */
#define CPU_FLASH_BASE FLASH_BASE /**< cpu flash base */
#define CPU_SPEED 80000000 /**< cpu speed */
#ifdef __cplusplus
}

77
cpu/cc3200/include/periph_cpu.h
View File

@ -17,7 +17,7 @@
* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
*/
#include "cc3200.h"
#include "cpu.h"
#include <stdbool.h>
#include <stdint.h>
@ -29,6 +29,38 @@
extern "C" {
#endif
/**
* @brief Override mode flank selection values
*
* @{
*/
#define HAVE_GPIO_FLANK_T
typedef enum {
GPIO_FALLING = 0, /**< emit interrupt on falling flank */
GPIO_BOTH = 1, /**< emit interrupt on both flanks */
GPIO_LOW = 2, /**< emit interrupt on low level */
GPIO_RISING = 4, /**< emit interrupt on rising flank */
GPIO_NONE = 5, /**< emit interrupt on rising flank */
GPIO_HIGH = 6 /**< emit interrupt on low level */
} gpio_flank_t;
/**
* @brief Starting offset of CPU_ID
*/
#define CPUID_ADDR (void *)(0xe000ed00)
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (4U)
/**
* @name Define a custom type for GPIO pins
* @{
*/
#define HAVE_GPIO_T
typedef uint32_t gpio_t;
/** @} */
#define TIMER_NUMOF (4U)
#define T0 TIMER_DEV(0U)
@ -62,16 +94,49 @@ extern "C" {
// } gpio_mode_t;
// /** @} */
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
#define CPUID_ADDR (void *)(0xe000ed00)
/**
* @brief Length of the CPU_ID in octets
* @name UART device configuration
* @{
*/
#define CPUID_LEN (4U)
typedef struct {
cc3200_uart_t *dev; /**< pointer to the used UART device */
gpio_t rx_pin; /**< pin used for RX */
gpio_t tx_pin; /**< pin used for TX */
gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using */
gpio_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using */
// gpio_t irqn /**< Interrupt code */
} uart_conf_t;
/** @} */
static const uart_conf_t uart_config[] = {
{
.dev = UART0,
// .freq = CLOCK_CORECLOCK,
// .pin_rx = GPIO_PIN(PORT_A, 14),
// .pin_tx = GPIO_PIN(PORT_A, 15),
// .pcr_rx = PORT_PCR_MUX(3),
// .pcr_tx = PORT_PCR_MUX(3),
// .irqn = UART0_RX_TX_IRQn,
// .scgc_addr = &SIM->SCGC4,
// .scgc_bit = SIM_SCGC4_UART0_SHIFT,
// .mode = UART_MODE_8N1,
},
{
.dev = UART1,
// .freq = CLOCK_CORECLOCK,
// .pin_rx = GPIO_PIN(PORT_C, 3),
// .pin_tx = GPIO_PIN(PORT_C, 4),
// .pcr_rx = PORT_PCR_MUX(3),
// .pcr_tx = PORT_PCR_MUX(3),
// .irqn = UART1_RX_TX_IRQn,
// .scgc_addr = &SIM->SCGC4,
// .scgc_bit = SIM_SCGC4_UART1_SHIFT,
// .mode = UART_MODE_8N1,
},
};
#ifdef __cplusplus
}
#endif

2
cpu/cc3200/include/vendor/rom.h vendored
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@ -42,10 +42,12 @@
// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND.
//
//*****************************************************************************
#include "vendor/hw_types.h"
#ifndef __ROM_H__
#define __ROM_H__
//*****************************************************************************
//
// Pointers to the main API tables.

496
cpu/cc3200/periph/gpio.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2019 Ludwig Maximilian Universität
* Copyright (C) 2019 Ludwig Maximilian Universität
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
@ -11,21 +11,24 @@
* @{
*
* @file
* @brief CPU specific definitions and functions for peripheral handling
* @brief CPU specific definitions and functions for peripheral
* handling
*
* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
*/
#include <stdint.h>
#include <stdbool.h>
#include <stdint.h>
#include "board.h"
#include "cpu.h"
#include "periph/gpio.h"
#include "periph_conf.h"
#include "sched.h"
#include "thread.h"
#include "periph/gpio.h"
#include "vendor/hw_gpio.h"
#include "board.h"
#include "periph_conf.h"
#include "vendor/hw_memmap.h"
#include "vendor/hw_ocp_shared.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
@ -45,404 +48,315 @@
static gpio_isr_ctx_t isr_ctx[4][8];
#endif /* MODULE_PERIPH_GPIO_IRQ */
#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \
OCP_SHARED_O_GPIO_PAD_CONFIG_0))
#define GPIO_PORT_MASK (0xfffff000) /**< bit mask for GPIO port addr */
#define NOT_A_PORT 0
#define NOT_A_PIN 0
#define NOT_A_GPIO 66
// GPIO PORTS
static unsigned long ulReg[]=
{
GPIOA0_BASE,
GPIOA1_BASE,
GPIOA2_BASE,
GPIOA3_BASE,
GPIOA4_BASE
};
#define PAD_MODE_MASK 0x0000000F
#define PAD_STRENGTH_MASK 0x000000E0
#define PAD_TYPE_MASK 0x00000310
#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0))
/**
* @brief PIN to PAD matrix
*
* @brief gpio base addresses
*
*/
static const unsigned long g_ulPinToPadMap[64] =
{
10, 11, 12, 13, 14, 15, 16, 17, 255, 255, 18,
19, 20, 21, 22, 23, 24, 40, 28, 29, 25, 255,
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
31, 255, 255, 255, 255, 0, 255, 32, 30, 255, 1,
255, 2, 3, 4, 5, 6, 7, 8, 9};
static unsigned long ports[] = {GPIOA0_BASE, GPIOA1_BASE, GPIOA2_BASE,
GPIOA3_BASE, GPIOA4_BASE};
static const unsigned long gpio_to_mcu_pin[32] = {
49, 54, 56, 57, 58, 59, 60, 61, 62, 63, 0, 1, 2, 3, 4, 5, 6, 7, NOT_A_GPIO, NOT_A_GPIO, NOT_A_GPIO, NOT_A_GPIO, 14, 15, 16, 20, NOT_A_GPIO, NOT_A_GPIO, 17, NOT_A_GPIO, 52, 44
};
/**
* @brief pin to GPIO pin numbers mappings
*
*/
static const unsigned long pin_to_gpio_num[64] = {
10, 11, 12, 13, 14, 15, 16, 17, 255, 255, 18, 19, 20,
21, 22, 23, 24, 40, 28, 29, 25, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
255, 255, 255, 255, 255, 31, 255, 255, 255, 255, 0, 255, 32,
30, 255, 1, 255, 2, 3, 4, 5, 6, 7, 8, 9};
/**
* @brief check if a port base is valid
*
* @param port
* @return true
* @return false
*
* @param port
* @return true
* @return false
*/
bool _gpioPortBaseValid(unsigned long port) {
return((port == GPIOA0_BASE) ||
(port == GPIOA1_BASE) ||
(port == GPIOA2_BASE) ||
(port == GPIOA3_BASE) ||
(port == GPIOA4_BASE));
bool _gpioPortBaseValid(unsigned long port) {
return ((port == GPIOA0_BASE) || (port == GPIOA1_BASE) ||
(port == GPIOA2_BASE) || (port == GPIOA3_BASE) ||
(port == GPIOA4_BASE));
}
/**
* @brief Extract the pin number of the given pin
*/
static inline uint8_t _pin_num(gpio_t pin)
{
return (pin & 0x3f);
}
static inline uint8_t _pin_num(gpio_t pin) { return (pin & 0x3f); }
/**
* @brief Extract the port number of the given pin
* @brief Extract the port number of a given pin
*/
static inline uint8_t _port_num(gpio_t pin)
{
return (pin >> 6) & 0x3;
}
static inline int8_t _mcu_pin_num(gpio_t pin) {
return gpio_to_mcu_pin[pin];
}
static inline uint8_t _port_num(gpio_t pin) { return (pin >> 6) & 0x3; }
/**
* @brief _gpio_pin_to_imux converts external pin numbers (e.g. printed on the board) to internal pin numbers
*
* @param dev
* @brief get pin mask for a given pin
*
* @param dev
* @return gpio pin offset for port
*/
uint8_t _gpio_pin_to_imux(uint8_t pin) {
return 1 << (pin % GPIO_PINS_PER_PORT);
uint8_t _gpio_pin_mask(uint8_t dev) {
return 1 << (pin_to_gpio_num[_pin_num(dev)] % GPIO_PINS_PER_PORT);
}
/**
* @brief _gpio_pin_to_port returns the port base address for a pin
*
*
* @param dev external pin number
* @return port base address
* @return port base address
*/
unsigned long _gpio_pin_to_port(uint8_t port) {
return ulReg[port];
}
unsigned long _gpio_pin_to_port(uint8_t port) { return ports[port]; }
/**
* @brief returns the masked value for a external pin
*
*
* @param pin external pin
* @param val value to be masked
* @return masked value for a given pin with value val
* @return masked value for a given pin with value val
*/
unsigned char _gpio_pin_value_mask(uint8_t pin, unsigned char val) {
return val << (pin % 8);
return val << (pin % 8);
}
/**
* @brief configure pin type and pin streng based on TIs pin.c/PinConfigGet
*
* @param pin
* @param strength
* @param type
* @brief Access GPIO low-level device
*
* @param[in] pin gpio pin
*
* @return pointer to gpio low level device address
*/
// void _set_pin_config(unsigned long pin, unsigned long type) {
// // get pin padding
// unsigned long pad = g_ulPinToPadMap[pin & 0x3F];
// if (type == GPIO_IN_ANALOG) {
// // isolate the input
// HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8));
static inline cc3200_gpio_t *gpio(gpio_t pin) {
return (cc3200_gpio_t *)(_gpio_pin_to_port(_port_num(pin)));
}
// // get register address
// ulPad = ((ulPad << 2) + PAD_CONFIG_BASE);
void gpio_init_af(gpio_t dev, uint32_t strength, uint32_t type) {
// does not support analog pin types, but not a problem for GPIO
uint8_t pin = _pin_num(dev);
uint8_t gpio_pin = pin_to_gpio_num[pin];
// // isolate the output
// HWREG(ulPad) = 0xC00;
// } else {
// // enable input
// // only for digital pins
// HWREG(0x4402E144) &= ~((0x80 << pad) & (0x1E << 8));
// copied from TIs PinConfigSet. The register is not documented so for now
// only replecate behaviour.
// // compute pin address
// pad = ((pad << 2) + PAD_CONFIG_BASE);
// enable input
HWREG(0x4402E144) &= ~((0x80 << gpio_pin) & (0x1E << 8));
// // write the configuration
// // 0x00000020 is PIN_STRENGTH_2MA
// // 0x00000000 is PIN_TYPE_STD
// // TODO: move constans
// HWREG(pad) = ((HWREG(pad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
// (0x00000020 | type));
// compute pin register
unsigned long regAddr = (gpio_pin << 2) + PAD_CONFIG_BASE;
// // set the pin mode
// HWREG(pad) = (((HWREG(pad) & ~PAD_MODE_MASK) | mode) & ~(3 << 10);
// }
// }
/**
* @brief set gpio to read or write mode
*
* @param portAddr base address of a GPIO port
* @param pins bitmap of which pins mode should be set
* @param inOrOut GPIO_IN | GPIO_OUT
*/
// void _set_gpio_dir_mode(unsigned portAddr, uint8_t pins, uint8_t inOrOut) {
// HWREG(portAddr + GPIO_O_GPIO_DIR) = ((inOrOut & 1) ?
// (HWREG(portAddr + GPIO_O_GPIO_DIR) | pins) :
// (HWREG(portAddr + GPIO_O_GPIO_DIR) & ~(pins)));
// }
// write config
HWREG(regAddr) = ((HWREG(regAddr) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
(strength | type));
}
/**
* @brief
*
* @param dev
* @param mode
* @return int
*/
int gpio_init(gpio_t dev, gpio_mode_t mode)
{
uint8_t port = _port_num(dev);
uint8_t pin = _pin_num(dev);
unsigned long mcuPinNum = _mcu_pin_num(pin);
void gpio_pin_mode_set(gpio_t dev, uint32_t mode) {
// does not support analog pin types, but not a problem for GPIO
uint8_t pin = _pin_num(dev);
uint8_t gpio_pin = pin_to_gpio_num[pin];
if (mcuPinNum == NOT_A_GPIO) {
return -1;
}
// compute pin register
unsigned long regAddr = (gpio_pin << 2) + PAD_CONFIG_BASE;
// get gpio port pin
uint8_t ipin = _gpio_pin_to_imux(pin);
unsigned long portAddr = _gpio_pin_to_port(port);
// set mode
HWREG(regAddr) = (((HWREG(regAddr) & ~PAD_MODE_MASK) | mode) & ~(3 << 10));
}
int gpio_init(gpio_t dev, gpio_mode_t mode) {
uint8_t pin = _pin_num(dev);
DEBUG("GPIO %"PRIu32", PORT: %u, PIN: %u\n", (uint32_t)dev, port, pin);
// get pin mask
uint8_t ipin = _gpio_pin_mask(dev);
// set pin to GPIO mode (does not to be done for only gpio pins but has no consequence and ist faster the reading first)
ROM_PinTypeGPIO(mcuPinNum, PIN_MODE_0, false);
// make sure pin is in the default state (this is quicker then reading first)
gpio_init_af(dev, PIN_STRENGTH_2MA, PIN_TYPE_STD);
gpio_pin_mode_set(dev, PIN_MODE_0);
// set gpio direction IN/OUT
if (mode == GPIO_OUT) {
gpio(dev)->dir |= ipin;
} else {
gpio(dev)->dir &= ipin;
}
// set gpio direction IN/OUT
if (mode == GPIO_OUT) {
ROM_GPIODirModeSet(portAddr, ipin, GPIO_DIR_MODE_OUT);
} else {
ROM_GPIODirModeSet(portAddr, ipin, GPIO_DIR_MODE_IN);
}
switch (mode) {
case GPIO_IN:
case GPIO_OUT:
case GPIO_OD:
gpio_init_af(dev, PIN_STRENGTH_2MA, PIN_TYPE_STD);
break;
case GPIO_OD_PU:
case GPIO_IN_PU:
gpio_init_af(dev, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU);
break;
case GPIO_IN_PD:
gpio_init_af(dev, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD);
break;
}
switch (mode) {
case GPIO_IN:
case GPIO_OUT:
case GPIO_OD:
MAP_PinConfigSet(mcuPinNum, PIN_STRENGTH_2MA, PIN_TYPE_STD);
break;
case GPIO_OD_PU:
case GPIO_IN_PU:
MAP_PinConfigSet(mcuPinNum, PIN_STRENGTH_2MA, PIN_TYPE_STD_PU);
break;
case GPIO_IN_PD:
MAP_PinConfigSet(mcuPinNum, PIN_STRENGTH_2MA, PIN_TYPE_STD_PD);
break;
}
return 0;
return 0;
}
#ifdef MODULE_PERIPH_GPIO_IRQ
void isr_gpio_a0(void)
{
handle_isr(GPIOA0_BASE);
}
void isr_gpio_a0(void) { handle_isr((cc3200_gpio_t *)GPIOA0_BASE); }
void isr_gpio_a1(void)
{
handle_isr(GPIOA1_BASE);
}
void isr_gpio_a1(void) { handle_isr((cc3200_gpio_t *)GPIOA1_BASE); }
void isr_gpio_a2(void)
{
handle_isr(GPIOA2_BASE);
}
void isr_gpio_a2(void) { handle_isr((cc3200_gpio_t *)GPIOA2_BASE); }
void isr_gpio_a3(void)
{
handle_isr(GPIOA3_BASE);
}
void isr_gpio_a3(void) { handle_isr((cc3200_gpio_t *)GPIOA3_BASE); }
/**
* @brief isr interrupt handler
*
*
* @param portAddr base address of the GPIO PORT
*/
void handle_isr(uint32_t portAddr)
{
uint32_t state = HWREG(portAddr + GPIO_O_GPIO_MIS);
void handle_isr(cc3200_gpio_t *u) {
uint32_t state = u->mis;
ROM_GPIOIntClear(portAddr, state);
// clear interrupt
u->icr = state;
for (int i = 0; i < 8; i++) {
if (state & (1 << i)) {
isr_ctx[port_num][i].cb(isr_ctx[port_num][i].arg);
}
}
for (int i = 0; i < 8; i++)
{
if (state & (1 << i)) {
isr_ctx[port_num][i].cb(isr_ctx[port_num][i].arg);
}
}
cortexm_isr_end();
}
/**
* @brief enable GPIO interrupt
* @param dev pin
*/
void gpio_irq_enable(gpio_t dev)
{
// uint8_t bit = _gpio_pin_to_imux(dev);
// uint8_t portAddr = _gpio_pin_to_port(dev);
// ROM_GPIOIntEnable(portAddr, bit);
cortexm_isr_end();
}
/**
* @brief disable GPIO interrupt
* @brief enable GPIO interrupt
* @param dev pin
*/
void gpio_irq_disable(gpio_t dev)
{
// uint8_t bit = _gpio_pin_to_imux(dev);
// uint8_t portAddr = _gpio_pin_to_port(dev);
// ROM_GPIOIntDisable(portAddr, bit);
}
void gpio_irq_enable(gpio_t dev) { gpio(dev)->im |= _gpio_pin_mask(dev); }
/**
* @brief disable GPIO interrupt
* @param dev pin
*/
void gpio_irq_disable(gpio_t dev) { gpio(dev)->im &= ~(_gpio_pin_mask(dev)); }
int gpio_init_int(gpio_t dev, gpio_mode_t mode, gpio_flank_t flank,
gpio_cb_t cb, void *arg)
{
gpio_cb_t cb, void *arg) {
/* Note: gpio_init() also checks if the gpio is enabled. */
int res = gpio_init(dev, mode);
if (res != 0) {
return res;
}
/* Note: gpio_init() also checks if the gpio is enabled. */
int res = gpio_init(dev, mode);
if (res != 0) {
return res;
}
uint8_t portNum = _port_num(dev);
uint8_t pinNum = _pin_num(dev);
uint8_t bit = _gpio_pin_to_imux(dev);
uint8_t portAddr = _gpio_pin_to_port(dev);
assert(flank != GPIO_NONE);
// store callback information;
isr_ctx[portNum][pinNum].cb = cb;
isr_ctx[portNum][pinNum].arg = arg;
uint8_t portNum = _port_num(dev);
uint8_t pinNum = _pin_num(dev);
uint8_t bit = _gpio_pin_mask(dev);
uint8_t portAddr = _gpio_pin_to_port(dev);
ROM_IntMasterDisable();
ROM_GPIOIntClear(portBase, bit);
// store callback information;
isr_ctx[portNum][pinNum].cb = cb;
isr_ctx[portNum][pinNum].arg = arg;
// configure active flanks
switch (flank) {
case GPIO_LOW:
ROM_GPIOIntTypeSet(portAddr, bit, 0x00000002);
break;
case GPIO_BOTH:
ROM_GPIOIntTypeSet(portAddr, bit, 0x00000001);
break;
case GPIO_RISING:
ROM_GPIOIntTypeSet(portAddr, bit, 0x00000004);
break;
case GPIO_FALLING:
ROM_GPIOIntTypeSet(portAddr, bit, 0x00000000);
break;
default:
return -1;
}
ROM_IntMasterDisable();
ROM_GPIOIntEnable(portAddr, bit);
// clear interrupt specified pin
gpio(dev)->ICR = bit;
switch (portBase) {
case GPIOA0_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a0);
ROM_IntEnable(INT_GPIOA0);
break;
case GPIOA1_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a1);
ROM_IntEnable(INT_GPIOA1);
break;
case GPIOA2_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a2);
ROM_IntEnable(INT_GPIOA2);
break;
case GPIOA3_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a3);
ROM_IntEnable(INT_GPIOA3);
break;
}
// configure active flanks
gpio(dev)->ibe =
(flank & GPIO_BOTH) ? gpio(dev)->ibe | bit : gpio(dev)->ibe & ~bit;
gpio(dev)->is =
(flank & GPIO_LOW) ? gpio(dev)->is | bit : gpio(dev)->is & ~bit;
gpio(dev)->iev =
(flank & GPIO_RISING) ? gpio(dev)->iev | bit : gpio(dev)->iev & ~bit;
ROM_IntMasterEnable();
// enable gpio interripts
gpio(dev)->im |= bit;
return 0;
// register interrupt handlers
// TODO: replace with cortex common
switch (portBase) {
case GPIOA0_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a0);
ROM_IntEnable(INT_GPIOA0);
break;
case GPIOA1_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a1);
ROM_IntEnable(INT_GPIOA1);
break;
case GPIOA2_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a2);
ROM_IntEnable(INT_GPIOA2);
break;
case GPIOA3_BASE:
ROM_GPIOIntRegister(portBase, isr_gpio_a3);
ROM_IntEnable(INT_GPIOA3);
break;
}
ROM_IntMasterEnable();
return 0;
}
#endif
/**
* @brief gpio_write writes to a GPIO pin dev (external) the value value
*
*
* @param dev external pin
* @param value value to be written (will be masked)
*/
void gpio_write(gpio_t dev, int value)
{
uint8_t port = _port_num(dev);
uint8_t pin = _pin_num(dev);
unsigned char ipin = _gpio_pin_to_imux(pin);
unsigned long portAddr = _gpio_pin_to_port(port);
// write to pin at portBase + pinOffset
HWREG(portAddr + (0x00000000 + (ipin << 2))) = _gpio_pin_value_mask(pin,value);
void gpio_write(gpio_t dev, int value) {
uint8_t port = _port_num(dev);
unsigned char ipin = _gpio_pin_mask(dev);
unsigned long portAddr = _gpio_pin_to_port(port);
// write to pin at portBase + pinOffset
HWREG(portAddr + (0x00000000 + (ipin << 2))) =
_gpio_pin_value_mask(pin_to_gpio_num[_pin_num(dev)], value);
}
/**
* @brief read a pins value
*
*
* @param dev external pin
* @return int current value of a pin
*/
int gpio_read(gpio_t dev)
{
uint8_t port = _port_num(dev);
uint8_t pin = _pin_num(dev);
unsigned char ipin = _gpio_pin_to_imux(pin);
unsigned long portAddr = _gpio_pin_to_port(port);
int gpio_read(gpio_t dev) {
uint8_t port = _port_num(dev);
unsigned char ipin = _gpio_pin_mask(dev);
unsigned long portAddr = _gpio_pin_to_port(port);
// read from pin at portBase + pinOffset
// cast value to int {0, 1}
return (HWREG(portAddr + (0x00000000 + (ipin << 2))) ? HIGH : LOW);
// read from pin at portBase + pinOffset
// cast value to int {0, 1}
return (HWREG(portAddr + (0x00000000 + (ipin << 2))) ? HIGH : LOW);
}
/**
* @brief set a pins value to HIGH (1)
*
*
* @param dev external pin
*/
void gpio_set(gpio_t dev)
{
gpio_write(dev, HIGH);
}
void gpio_set(gpio_t dev) { gpio_write(dev, HIGH); }
/**
* @brief set a pins value to LOW (0)
*
*
* @param dev external pin
*/
void gpio_clear(gpio_t dev)
{
gpio_write(dev, LOW);
}
void gpio_clear(gpio_t dev) { gpio_write(dev, LOW); }
/**
* @brief toggle a gpio pins value
*
*
* @param dev external pin
*/
void gpio_toggle(gpio_t dev)
{
gpio_read(dev) ? gpio_clear(dev) : gpio_set(dev);
void gpio_toggle(gpio_t dev) {
gpio_read(dev) ? gpio_clear(dev) : gpio_set(dev);
}

32
cpu/cc3200/periph/pm.c
View File

@ -6,33 +6,21 @@
* directory for more details.
*/
#include "driverlib/rom_map.h"
#include "periph/pm.h"
#include "vendor/rom.h"
#ifdef PROVIDES_PM_SET_LOWEST_CORTEXM
// TODO: needs to be impemented
void pm_set_lowest(void)
{
/* this will hibernate with no way to wake up for now */
// write to the hibernate register
HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ) = 0x1;
// TODO: needs to be impemented
void pm_set_lowest(void) {
/* this will hibernate with no way to wake up for now */
// wait for 200 uSec
UtilsDelay((80*200)/3);
// write to the hibernate register
HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REQ) = 0x1;
// wait for 200 uSec
UtilsDelay((80 * 200) / 3);
}
#endif
void pm_off(void)
{
/* No Generic Power off Mechanism */
void pm_off(void) { /* No Generic Power off Mechanism */
}
// wait based on 3 cycles of the CPU
void __attribute__((naked))
delay(unsigned long ulCount)
{
__asm(" subs r0, #1\n"
" bne delay\n"
" bx lr");
}

215
cpu/cc3200/periph/spi.c
View File

@ -1,23 +1,24 @@
/*
* Copyright (C) 2015 Attilio Dona'
* Copyright (C) 2019 Ludwig Maximilian Universität
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_cc3200
* @defgroup cpu_cc3200_gpio CC3200 General-Purpose I/O
* @ingroup cpu_cc3200_regs
* @{
*
* @file
* @brief Low-level SPI driver implementation
* @brief Driver for the cc3200 GPIO controller
*
* @author Attilio Dona' <@attiliodona>
*
* @}
* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
*
* @{
*/
#include "periph/spi.h"
#include "board.h"
#include "cpu.h"
@ -25,13 +26,10 @@
#include "periph/gpio.h"
#include "periph_conf.h"
#include "driverlib/pin.h"
#include "driverlib/prcm.h"
#include "driverlib/spi.h"
#include "driverlib/utils.h"
#include "vendor/hw_ints.h"
#include "vendor/hw_mcspi.h"
#include "vendor/hw_udma.h"
#include "vendor/rom.h"
#define ENABLE_DEBUG (0)
#include "debug.h"
/**
@ -44,16 +42,20 @@
// #define SPI_NUMOF 2U
#define EXTERNAL_SPI 0U
#define CC3100_SPI 1U
#define XTAL_CLK 40000000
static const spi_conf_t spi_config[] = {
{
.base_addr = GSPI_BASE,
.gpio_port = 0,
.pins =
(spi_pins_t){
.miso = PIN_06, .sck = PIN_05, .mosi = PIN_07, .cs = PIN_08},
},
{.base_addr = LSPI_BASE, .gpio_port = 1}};
{.base_addr = GSPI_BASE,
.gpio_port = 0,
.pins =
(spi_pins_t){
.miso = PIN_06, .sck = PIN_05, .mosi = PIN_07, .cs = PIN_08},
.config = (SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
SPI_CS_ACTIVELOW | SPI_WL_8)},
{.base_addr = LSPI_BASE,
.gpio_port = 1,
.config = (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH | SPI_WL_32)}};
/**
* @brief Allocate one lock per SPI device
@ -64,9 +66,6 @@ void spi_init_pins(spi_t bus) {
switch (bus) {
case EXTERNAL_SPI:
// enable peripherial clock
MAP_PRCMPeripheralClkEnable(PRCM_GSPI, PRCM_RUN_MODE_CLK);
// TODO: use gpio_init for this when PIN_MODE mapping is done
// GSPI_CLK
ROM_PinTypeSPI(spi_config[bus].pins.sck, PIN_MODE_7);
// set MISO pin
@ -84,21 +83,85 @@ void spi_init_pins(spi_t bus) {
}
}
void enable_peiph_clk(unsigned long bus, unsigned long mask) {
MAP_PRCMPeripheralClkEnable(bus, mask);
static inline cc3200_spi_t *spi(uint32_t baseAddr) {
return (cc3200_spi_t *)baseAddr;
}
static inline uint32_t get_word_len(uint32_t conf) {
// use WL_32 as mask
return conf | SPI_WL_32;
}
/**
* @brief reset spi to default state
*
* @param bus spi bus id
*/
void spi_reset(spi_t bus) {
// Disable Chip Select
ROM_SPICSDisable(spi_config[bus].base_addr);
volatile cc3200_spi_t *dev = spi(spi_config[bus].base_addr);
// disable chip select in software controlled mode
dev->ch0_conf &= ~MCSPI_CH0CONF_FORCE;
// Disable SPI Channel
ROM_SPIDisable(spi_config[bus].base_addr);
dev->ch0_ctrl &= ~MCSPI_CH0CTRL_EN;
// reset SPI
ROM_SPIReset(spi_config[bus].base_addr);
dev->sys_conf |= MCSPI_SYSCONFIG_SOFTRESET;
ROM_SPIEnable(spi_config[bus].base_addr);
// wait for reset
while (!((dev->sys_status) & MCSPI_SYSSTATUS_RESETDONE)) {
}
// enable spi
dev->ch0_ctrl &= ~MCSPI_CH0CTRL_EN;
}
/**
* @brief configure spi module. This functions is closely modeled after
* SPIConfigSetExpClk.
*
* @param bus
* @param mode SPI operation sub mode
* @param clk SPI bit rate
*/
void _spi_config(spi_t bus, spi_mode_t mode, spi_clk_t clk) {
volatile cc3200_spi_t *dev = spi(spi_config[bus].base_addr);
// current value of the ctrl register is used as a starting point
cc3200_reg_t tmp = dev->module_ctrl;
// compute divider value
cc3200_reg_t divider = (XTAL_CLK / clk) - 1;
// set master mode with hardware chip select
tmp &= ~(MCSPI_MODULCTRL_MS | MCSPI_MODULCTRL_SINGLE);
// set SPI config
// TIs code is also using OR with Master/Slave mode
// since riot only supports master mode we can skip that
tmp |= (spi_config[bus].config >> 24) & 0xFF;
// write config
dev->module_ctrl = tmp;
// reset tmp and set IS, DPE0, DPE1 for master mode
tmp = 0x1 << 16;
// mask config and set clock divider granularity to 1 cycle
tmp &= ~(MCSPI_CH0CONF_WL_M | MCSPI_CH0CONF_EPOL | MCSPI_CH0CONF_POL |
MCSPI_CH0CONF_PHA | MCSPI_CH0CONF_TURBO);
tmp |= MCSPI_CH0CONF_CLKG;
//
// The least significant four bits of the divider is used fo configure
// CLKD in MCSPI_CHCONF next eight least significant bits are used to
// configure the EXTCLK in MCSPI_CHCTRL
//
tmp |= ((divider & 0x0000000F) << 2);
dev->ch0_ctrl = ((divider & 0x00000FF0) << 4);
// set protocol, CS polarity, word length and turbo mode
dev->ch0_conf = ((tmp | mode) | (spi_config[bus].config & 0x0008FFFF));
}
void spi_init(spi_t bus) {
@ -111,10 +174,10 @@ void spi_init(spi_t bus) {
// enable clock
switch (bus) {
case EXTERNAL_SPI:
enable_peiph_clk(PRCM_GSPI, PRCM_RUN_MODE_CLK);
ARCM->MCSPI_A1.clk_gating |= PRCM_RUN_MODE_CLK;
break;
case CC3100_SPI:
enable_peiph_clk(PRCM_LSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
ARCM->MCSPI_A2.clk_gating |= PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK;
break;
}
@ -129,24 +192,8 @@ int spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk) {
if (bus >= SPI_UNDEF)
return -1;
// TODO: use cs mode and clock for now only master is supported with the
// default clocks enable clock
switch (bus) {
case EXTERNAL_SPI:
MAP_SPIConfigSetExpClk(spi_config[bus].base_addr,
ROM_PRCMPeripheralClockGet(PRCM_GSPI), clk,
SPI_MODE_MASTER, mode,
(SPI_HW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
SPI_CS_ACTIVELOW | SPI_WL_8));
break;
case CC3100_SPI:
MAP_SPIConfigSetExpClk(spi_config[bus].base_addr,
ROM_PRCMPeripheralClockGet(PRCM_LSPI), clk,
SPI_MODE_MASTER, mode,
(SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH | SPI_WL_32));
break;
}
_spi_config(bus, mode, clk);
return 0;
}
@ -163,14 +210,58 @@ uint8_t spi_transfer_byte(spi_t bus, spi_cs_t cs, bool cont, uint8_t out) {
void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont, const void *out,
void *in, size_t len) {
if (bus >= SPI_NUMOF) {
return;
}
// ROM_SPITransfer(GSPI_BASE, (unsigned char*)out, (unsigned char*)in, length,
// SPI_CS_ENABLE|SPI_CS_DISABLE);
DEBUG("%s: bus=%u, len=%u\n", __FUNCTION__, bus, (unsigned)len);
ROM_SPITransfer(spi_config[bus].base_addr, (unsigned char *)out,
(unsigned char *)in, len, 0);
// // check that at least read or write buffer is set
// assert(in || out);
// // initialize icrements for read and write buffers
// size_t writeIncr = out == NULL ? 0 : 1;
// size_t readIncr = in == NULL ? 0 : 1;
// // check if data size is compatible with SPI word length and adjust length
// switch (get_word_len(spi_config[bus].config)) {
// case SPI_WL_32:
// assert(!(len % 4));
// writeIncr *= 4;
// readIncr *= 4;
// break;
// case SPI_WL_16:
// assert(!(len % 2));
// writeIncr *= 2;
// readIncr *= 2;
// break;
// }
// cc3200_spi_t *dev = spi(spi_config[bus].base_addr);
// // if (cs != SPI_CS_UNDEF) {
// // gpio_clear((gpio_t)cs);
// // }
// // enable cs flags
// // dev->ch0_conf |= MCSPI_CH0CONF_FORCE;
// while (len) {
// // send one word of data
// while (!(dev->ch0_stat & MCSPI_CH0STAT_TXS)) {
// }
// dev->tx0 = *((uint32_t *)out);
// // read one word of response
// while (!(dev->ch0_stat & MCSPI_CH0STAT_RXS)) {
// }
// *((uint32_t *)in) = dev->rx0;
// // increment pointers
// out += writeIncr;
// in += readIncr;
// }
// ROM_SPITransfer(GSPI_BASE, (unsigned char*)out, (unsigned char*)in,
// length, SPI_CS_ENABLE|SPI_CS_DISABLE);
// ROM_SPITransfer(spi_config[bus].base_addr, (unsigned char *)out,
// (unsigned char *)in, len, 0);
}
uint8_t spi_transfer_reg(spi_t bus, spi_cs_t cs, uint8_t reg, uint8_t out) {
@ -180,8 +271,8 @@ uint8_t spi_transfer_reg(spi_t bus, spi_cs_t cs, uint8_t reg, uint8_t out) {
// ROM_SPITransfer(GSPI_BASE, &reg, 0, 1, SPI_CS_ENABLE);
ROM_SPITransfer(spi_config[bus].base_addr, &reg, 0, 1, 0);
// if (ROM_SPITransfer(GSPI_BASE, (unsigned char*)&out, (unsigned char*)in, 1,
// SPI_CS_DISABLE)) {
// if (ROM_SPITransfer(GSPI_BASE, (unsigned char*)&out, (unsigned char*)in,
// 1, SPI_CS_DISABLE)) {
if (ROM_SPITransfer(spi_config[bus].base_addr, (unsigned char *)&out, 0, 1,
0)) {
return -1;
@ -203,7 +294,3 @@ void spi_transfer_regs(spi_t bus, spi_cs_t cs, uint8_t reg, const void *out,
return;
}
}
void spi_transmission_begin(spi_t dev, char reset_val) {
/* spi slave is not implemented */
}

96
cpu/cc3200/periph/timer.c
View File

@ -26,11 +26,12 @@
#include "periph_conf.h"
#include "xtimer.h"
#include "driverlib/rom.h"
// #include "driverlib/rom.h"
#include "vendor/hw_ints.h"
#include "vendor/hw_memmap.h"
#include "vendor/hw_timer.h"
#include "vendor/hw_types.h"
#include "vendor/rom.h"
//*****************************************************************************
//
@ -38,16 +39,16 @@
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
@ -55,10 +56,9 @@
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
@ -66,32 +66,34 @@
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP \
0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP \
0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
#define MAX_TIMERS TIMER_NUMOF
@ -194,9 +196,8 @@ static inline void *getHandler(tim_t dev) {
};
}
#define ROM_TimerConfigure \
((void (*)(unsigned long ulBase, \
unsigned long ulConfig))ROM_TIMERTABLE[2])
#define ROM_TimerConfigure \
((void (*)(unsigned long ulBase, unsigned long ulConfig))ROM_TIMERTABLE[2])
int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg) {
@ -211,11 +212,10 @@ int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg) {
uint32_t base = (int)timer_config[dev].timer;
// enable periph clock
MAP_PRCMPeripheralClkEnable(timer_config[dev].periph_id, PRCM_RUN_MODE_CLK);
// reset timer
MAP_PRCMPeripheralReset(timer_config[dev].periph_id);
// enable & reset periph clock
cc3200_periph_regs_t *periphReg =
((cc3200_periph_regs_t **)ARCM)[timer_config[dev].periph_id];
init_periph_clk(periphReg);
// setup timer
ROM_TimerConfigure(base, TIMER_CFG_PERIODIC_UP);

476
cpu/cc3200/periph/uart.c
View File

@ -26,48 +26,31 @@
#include "periph_conf.h"
#include "sched.h"
#include "thread.h"
#include "xtimer.h"
#include "vendor/hw_uart.h"
#include "vendor/rom.h"
#include "xtimer.h"
#define UNUSED(x) ((x) = (x))
// FIXME: don't know why this is needed (ROM_IntEnable should be already present)
#define ROM_IntEnable \
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
#define SYS_CLK 80000000
/**
* Define the nominal CPU core clock
*/
#define F_CPU 80000000
/* Bit masks for the UART Masked Interrupt Status (MIS) Register: */
#define OEMIS (1 << 10) /**< UART overrun errors */
#define BEMIS (1 << 9) /**< UART break error */
#define FEMIS (1 << 7) /**< UART framing error */
#define RTMIS (1 << 6) /**< UART RX time-out */
#define RXMIS (1 << 4) /**< UART RX masked interrupt */
#define SEC_TO_TICKS(sec) 80000000 * sec /**< Convert seconds to clock ticks \
*/
#define MSEC_TO_TICKS(msec) \
80000 * msec /**< Convert millisecs to clock ticks */
#define USEC_TO_TICKS(usec) \
80 * usec /**< Convert microseconds to clock ticks */
/* guard file in case no UART device was specified */
#if UART_NUMOF
/*---------------------------------------------------------------------------*/
/**
* @brief Each UART device has to store two callbacks.
*/
typedef struct {
uart_rx_cb_t rx_cb;
void *arg;
} uart_conf_t;
int uart_init_blocking(uart_t uart, uint32_t baudrate);
// FIXME: don't know why this is needed (ROM_IntEnable should be already
// present)
#define ROM_IntEnable \
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
/**
* @brief Allocate memory to store the callback functions.
*/
static uart_conf_t uart_config[UART_NUMOF];
static uart_isr_ctx_t uart_ctx[UART_NUMOF];
/*---------------------------------------------------------------------------*/
static void reset(unsigned long uart_base) {
MAP_UARTDisable(uart_base);
MAP_UARTRxErrorClear(uart_base);
@ -75,65 +58,154 @@ static void reset(unsigned long uart_base) {
MAP_UARTFIFODisable(uart_base);
}
/*---------------------------------------------------------------------------*/
void _uart_disable(uart_t uart) {
volatile cc3200_uart_t *reg = uart_config[uart].dev;
#if UART_0_EN
void isr_uart0(void) {
MAP_UARTIntClear(UARTA0_BASE, UART_INT_RX | UART_INT_OE | UART_INT_BE |
UART_INT_PE | UART_INT_FE);
if (MAP_UARTRxErrorGet(UARTA0_BASE)) {
reset(UARTA0_BASE);
} else {
long data;
data = MAP_UARTCharGetNonBlocking(UARTA0_BASE);
if (data != -1) {
uart_config[0].rx_cb(uart_config[0].arg, data);
}
// wait for uart to finish
while (reg->flags.bits.BUSY) {
}
if (sched_context_switch_request) {
thread_yield();
}
// disable fifo
reg->LCRH.bits.FEN = 0;
// disable the uart
reg->CTL.raw &= ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
}
#endif /* UART_0_EN */
#if UART_1_EN
void isr_uart1(void) {
MAP_UARTIntClear(UARTA1_BASE, UART_INT_RX | UART_INT_OE | UART_INT_BE |
UART_INT_PE | UART_INT_FE);
void _uart_enable(uart_t uart) {
volatile cc3200_uart_t *reg = uart_config[uart].dev;
if (UARTRxErrorGet(UARTA1_BASE)) {
reset(UARTA1_BASE);
} else {
long data;
// enable FIFO
reg->LCRH.bits.FEN = 1;
data = MAP_UARTCharGetNonBlocking(UARTA1_BASE);
if (data != -1) {
uart_config[1].rx_cb(uart_config[1].arg, data);
}
}
if (sched_context_switch_request) {
thread_yield();
}
// enable TX, RX and UART
reg->CTL.raw |= (UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
}
void _uart_config(uart_t uart, uint32_t baudrate, uint32_t config) {
// stop uart
_uart_disable(uart);
volatile cc3200_uart_t *reg = uart_config[uart].dev;
uint32_t div;
// check if baudrate is too high and needs high speed mode
if ((baudrate * 16) > SYS_CLK) {
reg->CTL.bits.HSE = 1;
// half the baudrate to compensate high speed mode
baudrate /= 2;
} else {
// disable high speed mode
reg->CTL.bits.HSE = 0;
}
// compute & set fractional baud rate divider
div = (((SYS_CLK * 8) / baudrate) + 1) / 2;
reg->IBRD = div / 64;
reg->FBRD = div % 64;
// set config
reg->LCRH.raw = config;
// clear flags
reg->flags.raw = 0;
_uart_enable(uart);
}
void irq_handler(uart_t uart) {
assert(uart < UART_NUMOF);
volatile cc3200_uart_t *reg = uart_config[uart].dev;
// get masked interrupt flags
uint16_t mis = uart_config[uart].dev->MIS.raw;
// clear the interrupt
reg->ICR = mis;
// read data
while (uart_config[uart].dev->flags.bits.RXFE == 0) {
uart_ctx[uart].rx_cb(uart_ctx[uart].arg, uart_config[uart].dev->dr);
}
if (mis & (OEMIS | BEMIS | FEMIS)) {
// clear error status
reg->cc3200_uart_dr.ecr = 0xFF;
}
cortexm_isr_end();
}
#if UART_0_ISR
void isr_uart0(void) { irq_handler((uart_t)0); }
#endif
#if UART_1_ISR
void isr_uart1(void) { irq_handler((uart_t)1); }
#endif /* UART_1_EN */
int uart_init_blocking(uart_t uart, uint32_t baudrate) {
cc3200_periph_regs_t *periphReg;
switch (uart) {
#if UART_0_EN
case UART_0:
init_periph_clk(&ARCM->UART_A0);
ARCM->UART_A0.clk_gating |= PRCM_RUN_MODE_CLK;
//
// Configure PIN_55 for UART0 UART0_TX
//
MAP_PinTypeUART(PIN_55, PIN_MODE_3);
//
// Configure PIN_57 for UART0 UART0_RX
//
MAP_PinTypeUART(PIN_57, PIN_MODE_3);
_uart_config(
uart, baudrate,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
reset(UARTA0_BASE);
break;
#endif
#if UART_1_EN
case UART_1:
init_periph_clk(&ARCM->UART_A1);
ARCM->UART_A1.clk_gating |= PRCM_RUN_MODE_CLK;
//
// Configure PIN_07 for UART1 UART1_TX
//
PinTypeUART(PIN_07, PIN_MODE_5);
//
// Configure PIN_08 for UART1 UART1_RX
//
PinTypeUART(PIN_08, PIN_MODE_5);
_uart_config(
uart, baudrate,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
reset(UARTA1_BASE);
break;
#endif
default:
return -1;
}
_uart_config(
uart, baudrate,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
return 0;
}
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) {
/* initialize basic functionality */
int res = uart_init_blocking(uart, baudrate);
if (res != 0) {
return res;
}
/* register callbacks */
uart_config[uart].rx_cb = rx_cb;
uart_config[uart].arg = arg;
/* configure interrupts and enable RX interrupt */
switch (uart) {
#if UART_0_EN
@ -155,227 +227,51 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg) {
}
return 0;
// volatile cc3200_uart_t *reg = uart_config[uart].dev;
// if (res != 0) {
// return res;
// }
// /* register callbacks */
// uart_ctx[uart].rx_cb = rx_cb;
// uart_ctx[uart].arg = arg;
// // enable uart interrupt
// reg->IM.raw |=
// UART_INT_RX | UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE;
// /* configure interrupts and enable RX interrupt */
// switch (uart) {
// #if UART_0_EN
// case UART_0:
// ROM_IntPrioritySet(INT_UARTA0, UART_IRQ_PRIO);
// ROM_IntEnable(INT_UARTA0);
// break;
// #endif
// #if UART_1_EN
// case UART_1:
// MAP_IntPrioritySet(INT_UARTA1, UART_IRQ_PRIO);
// ROM_IntEnable(INT_UARTA1);
// break;
// #endif
// }
// return 0;
}
int uart_init_blocking(uart_t uart, uint32_t baudrate) {
switch (uart) {
#if UART_0_EN
case UART_0:
MAP_PRCMPeripheralReset(PRCM_UARTA0);
//
// Enable Peripheral Clocks
//
MAP_PRCMPeripheralClkEnable(PRCM_UARTA0, PRCM_RUN_MODE_CLK);
//
// Configure PIN_55 for UART0 UART0_TX
//
MAP_PinTypeUART(PIN_55, PIN_MODE_3);
//
// Configure PIN_57 for UART0 UART0_RX
//
MAP_PinTypeUART(PIN_57, PIN_MODE_3);
MAP_UARTConfigSetExpClk(
UARTA0_BASE, MAP_PRCMPeripheralClockGet(PRCM_UARTA0), baudrate,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
reset(UARTA0_BASE);
break;
#endif
#if UART_1_EN
case UART_1:
//
// Enable Peripheral Clocks
//
PRCMPeripheralClkEnable(PRCM_UARTA1, PRCM_RUN_MODE_CLK);
//
// Configure PIN_07 for UART1 UART1_TX
//
PinTypeUART(PIN_07, PIN_MODE_5);
//
// Configure PIN_08 for UART1 UART1_RX
//
PinTypeUART(PIN_08, PIN_MODE_5);
MAP_UARTConfigSetExpClk(
UARTA1_BASE, MAP_PRCMPeripheralClockGet(PRCM_UARTA1), baudrate,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
reset(UARTA1_BASE);
break;
#endif
default:
return -1;
}
return 0;
}
void uart_tx_begin(uart_t uart) { UNUSED(uart); }
void uart_tx_end(uart_t uart) { UNUSED(uart); }
void uart_write(uart_t uart, const uint8_t *data, size_t len) {
unsigned long u;
#ifdef CUSTOM_WRITE_R
uart_remote(data, len);
#endif
switch (uart) {
#if UART_0_EN
case UART_0:
u = UARTA0_BASE;
break;
#endif
#if UART_1_EN
case UART_1:
u = UARTA1_BASE;
break;
#endif
default:
return;
}
volatile cc3200_uart_t *u = uart_config[uart].dev;
/* Block if the TX FIFO is full */
for (size_t i = 0; i < len; i++) {
MAP_UARTCharPut(u, data[i]);
ROM_UARTCharPut((unsigned long)u, data[i]);
// while (u->flags.bits.TXFF) {
// }
// u->dr = data[i];
}
}
int uart_read_blocking(uart_t uart, char *data) {
unsigned long u;
switch (uart) {
#if UART_0_EN
case UART_0:
u = UARTA0_BASE;
break;
#endif
#if UART_1_EN
case UART_1:
u = UARTA1_BASE;
break;
#endif
default:
return -1;
}
*data = MAP_UARTCharGet(u);
return 1;
}
/**
* @brief Get the Command string from UART
*
* @param pucBuffer is the command store to which command will be populated
* @param ucBufLen is the length of buffer store available
*
* @return Length of the bytes received. -1 if buffer length exceeded.
*
**/
int uart_read_line(uart_t uart, char *pcBuffer, unsigned int uiBufLen) {
char cChar;
unsigned int iLen = 0;
unsigned long CONSOLE;
switch (uart) {
#if UART_0_EN
case UART_0:
CONSOLE = UARTA0_BASE;
break;
#endif
#if UART_1_EN
case UART_1:
CONSOLE = UARTA1_BASE;
break;
#endif
default:
return -1;
}
//
// Wait to receive a character over UART
//
while (MAP_UARTCharsAvail(CONSOLE) == false) {
xtimer_usleep(MSEC_TO_TICKS(1));
}
cChar = MAP_UARTCharGetNonBlocking(CONSOLE);
//
// Echo the received character
//
MAP_UARTCharPut(CONSOLE, cChar);
iLen = 0;
//
// Checking the end of Command
//
while ((cChar != '\r') && (cChar != '\n')) {
//
// Handling overflow of buffer
//
if (iLen >= uiBufLen) {
return -1;
}
//
// Copying Data from UART into a buffer
//
if (cChar != '\b') {
*(pcBuffer + iLen) = cChar;
iLen++;
} else {
//
// Deleting last character when you hit backspace
//
if (iLen) {
iLen--;
}
}
//
// Wait to receive a character over UART
//
while (MAP_UARTCharsAvail(CONSOLE) == false) {
xtimer_usleep(MSEC_TO_TICKS(1));
}
cChar = MAP_UARTCharGetNonBlocking(CONSOLE);
//
// Echo the received character
//
MAP_UARTCharPut(CONSOLE, cChar);
}
*(pcBuffer + iLen) = '\0';
MAP_UARTCharPut(CONSOLE, '\n');
MAP_UARTCharPut(CONSOLE, '\r');
return iLen;
}
int uart_write_blocking(uart_t uart, char data) {
UNUSED(uart);
MAP_UARTCharPut(UARTA0_BASE, data);
return 1;
}
// TODO: enable power off and on after PWD SYS is ported
void uart_poweron(uart_t uart) { UNUSED(uart); }
void uart_poweroff(uart_t uart) { UNUSED(uart); }
#endif /* UART_NUMOF */

2
examples/wifi/cmd.c
View File

@ -99,7 +99,7 @@ uint8_t sendCommand(DriverMessage *msg, DriverResponse *res) {
int i;
// TODO: may lead to problems in multithreaded envs
for (i = CMD_TIMEOUT; req.Waiting && (i > 0); i--) {
UtilsDelay(80 * 50000 / 3);
delay(80 * 50000 / 3);
}
if (i == 0 && req.Waiting) {

117
examples/wifi/driver.c
View File

@ -4,13 +4,14 @@
#include "vendor/hw_types.h"
#include "vendor/hw_udma.h"
#include "cc3200_spi.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin.h"
#include "driverlib/prcm.h"
#include "driverlib/rom_map.h"
#include "driverlib/spi.h"
#include "driverlib/utils.h"
// #include "cc3200_spi.h"
#include "periph/spi.h"
// #include "driverlib/interrupt.h"
// #include "driverlib/pin.h"
// #include "driverlib/prcm.h"
// #include "driverlib/rom_map.h"
// #include "driverlib/spi.h"
// #include "driverlib/utils.h"
#include "proto.h"
#include "protocol.h"
@ -20,73 +21,75 @@
#include <stdbool.h>
#include <stdio.h>
static volatile cc3200_spi_t *wifiReg = (struct cc3200_spi_t *)WIFI_SPI_BASE;
// static volatile cc3200_spi_t *wifiReg = (struct cc3200_spi_t *)WIFI_SPI_BASE;
const _SlSyncPattern_t g_H2NSyncPattern = CPU_TO_NET_CHIP_SYNC_PATTERN;
const _SlSyncPattern_t g_H2NCnysPattern = CPU_TO_NET_CHIP_CNYS_PATTERN;
static uint32_t TxSeqNum = 0;
int read(uint8_t *buf, int len) {
unsigned long ulCnt;
unsigned long *ulDataIn;
spi_transfer_bytes(1, SPI_CS_UNDEF, true, NULL, buf, len);
// unsigned long ulCnt;
// unsigned long *ulDataIn;
MAP_SPICSEnable((int)wifiReg);
// MAP_SPICSEnable((int)wifiReg);
//
// Initialize local variable.
//
ulDataIn = (unsigned long *)buf;
ulCnt = (len + 3) >> 2;
// //
// // Initialize local variable.
// //
// ulDataIn = (unsigned long *)buf;
// ulCnt = (len + 3) >> 2;
//
// Reading loop
//
while (ulCnt--) {
while (!(wifiReg->stat & MCSPI_CH0STAT_TXS))
;
wifiReg->tx0 = 0xFFFFFFFF;
while (!(wifiReg->stat & MCSPI_CH0STAT_RXS))
;
*ulDataIn = wifiReg->rx0;
ulDataIn++;
}
// //
// // Reading loop
// //
// while (ulCnt--) {
// while (!(wifiReg->ch0_stat & MCSPI_CH0STAT_TXS))
// ;
// wifiReg->tx0 = 0xFFFFFFFF;
// while (!(wifiReg->ch0_stat & MCSPI_CH0STAT_RXS))
// ;
// *ulDataIn = wifiReg->rx0;
// ulDataIn++;
// }
MAP_SPICSDisable((int)wifiReg);
// MAP_SPICSDisable((int)wifiReg);
return len;
}
int send(uint8_t *in, int len) {
unsigned long ulCnt;
unsigned long *ulDataOut;
unsigned long ulDataIn = 0;
spi_transfer_bytes(1, SPI_CS_UNDEF, true, in, NULL, len);
// unsigned long ulCnt;
// unsigned long *ulDataOut;
// unsigned long ulDataIn = 0;
// enable spi
MAP_SPICSEnable(WIFI_SPI_BASE);
// // enable spi
// MAP_SPICSEnable(WIFI_SPI_BASE);
ulDataOut = (unsigned long *)in;
ulCnt = (len + 3) >> 2;
// ulDataOut = (unsigned long *)in;
// ulCnt = (len + 3) >> 2;
//
// Writing Loop
//
while (ulCnt--) {
// send one word of data
while (!(wifiReg->stat & MCSPI_CH0STAT_TXS))
;
wifiReg->tx0 = *ulDataOut;
// //
// // Writing Loop
// //
// while (ulCnt--) {
// // send one word of data
// while (!(wifiReg->ch0_stat & MCSPI_CH0STAT_TXS))
// ;
// wifiReg->tx0 = *ulDataOut;
// read one word of response
while (!(wifiReg->stat & MCSPI_CH0STAT_RXS))
;
ulDataIn = wifiReg->rx0;
// // read one word of response
// while (!(wifiReg->ch0_stat & MCSPI_CH0STAT_RXS))
// ;
// ulDataIn = wifiReg->rx0;
// increment pointers
ulDataOut++;
}
(void)ulDataIn;
// // increment pointers
// ulDataOut++;
// }
// (void)ulDataIn;
// disable spi again
MAP_SPICSDisable(WIFI_SPI_BASE);
// // disable spi again
// MAP_SPICSDisable(WIFI_SPI_BASE);
return len;
}
@ -152,7 +155,7 @@ void sendPowerOnPreamble(void) {
/* Perform the sl_stop equivalent to ensure network services
are turned off if active */
HWREG(0x400F70B8) = 1; /* APPs to NWP interrupt */
UtilsDelay(800000 / 5);
delay(800000 / 5);
retry_count = 0;
nwp_lpds_wake_cfg = HWREG(0x4402D404);
@ -165,7 +168,7 @@ void sendPowerOnPreamble(void) {
while (retry_count < 1000) {
apps_int_sts_raw = HWREG(0x400F70C0);
if (apps_int_sts_raw & 0x1) {
UtilsDelay(800000 / 5);
delay(800000 / 5);
retry_count++;
} else {
break;
@ -173,7 +176,7 @@ void sendPowerOnPreamble(void) {
}
}
HWREG(0x400F70B0) = 1; /* Clear APPs to NWP interrupt */
UtilsDelay(800000 / 5);
delay(800000 / 5);
powerOffWifi();
}

316
examples/wifi/main.c
View File

@ -21,7 +21,9 @@
#include <stdio.h>
#include <string.h>
#define ENABLE_DEBUG (1)
// #include "board.h"
#include "debug.h"
#include "cmd.h"
#include "driver.h"
@ -34,57 +36,52 @@
#include "utils.h"
#include "driverlib/utils.h"
#define RECEIVER (1)
#define WLAN_CHANNEL (13)
#define SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0)
#define SL_RAW_RF_TX_PARAMS_RATE_SHIFT (6)
#define SL_RAW_RF_TX_PARAMS_POWER_SHIFT (11)
#define SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15)
/* sockopt */
typedef _u32 SlTime_t;
typedef _u32 SlSuseconds_t;
#define SL_RAW_RF_TX_PARAMS(chan, rate, power, preamble) \
((chan << SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \
(rate << SL_RAW_RF_TX_PARAMS_RATE_SHIFT) | \
(power << SL_RAW_RF_TX_PARAMS_POWER_SHIFT) | \
(preamble << SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT))
typedef struct SlTimeval_t {
SlTime_t tv_sec; /* Seconds */
SlSuseconds_t tv_usec; /* Microseconds */
} SlTimeval_t;
#define SL_POLICY_CONNECTION (0x10)
#define SL_POLICY_SCAN (0x20)
#define SL_POLICY_PM (0x30)
#define SL_POLICY_P2P (0x40)
#define VAL_2_MASK(position, value) ((1 & (value)) << (position))
#define MASK_2_VAL(position, mask) (((1 << position) & (mask)) >> (position))
#define SL_CONNECTION_POLICY(Auto, Fast, Open, anyP2P, autoSmartConfig) \
(VAL_2_MASK(0, Auto) | VAL_2_MASK(1, Fast) | VAL_2_MASK(2, Open) | \
VAL_2_MASK(3, anyP2P) | VAL_2_MASK(4, autoSmartConfig))
#define SL_SCAN_POLICY_EN(policy) (MASK_2_VAL(0, policy))
#define SL_SCAN_POLICY(Enable) (VAL_2_MASK(0, Enable))
#define SL_NORMAL_POLICY (0)
#define SL_LOW_LATENCY_POLICY (1)
#define SL_LOW_POWER_POLICY (2)
#define SL_ALWAYS_ON_POLICY (3)
#define SL_LONG_SLEEP_INTERVAL_POLICY (4)
#define LED_RED GPIO_PIN(1, 9)
#define LED_ORANGE GPIO_PIN(1, 10)
#define LED_GREEN GPIO_PIN(1, 11)
const WifiCtrlCmd DeviceGetCommand = {
0x8466, // SL_OPCODE_DEVICE_DEVICEGET,
sizeof(_DeviceSetGet_t),
sizeof(_DeviceSetGet_t),
};
typedef struct wifi_80211_baseheader {
uint16_t fc; // frame control
uint16_t duration; // duration
uint8_t dest[6]; // destination MAC
uint8_t src[6]; // src MAC
uint8_t bssid[6]; // bssid MAC
uint16_t seq_ctl; // Sequence control
} wifi_80211_baseheader;
char RawData_Ping[] = {
// 0x88, 0x49, 0x30, 0x00, 0xe0, 0x28, 0x6d, 0xc8, 0x87, 0xe6, 0x7c, 0x49,
// 0xeb, 0x89, 0x08, 0x01, 0xe0, 0x28
// , 0x6d, 0xc8, 0x87, 0xe4, 0x30, 0x1d, 0x00, 0x00, 0x47, 0x16, 0x00, 0x20,
// 0x08, 0x00, 0x00, 0x00
// , 0x45, 0x6d, 0xd5, 0x95, 0xba, 0x84, 0x38, 0x65, 0xab, 0x78, 0xed, 0x9c,
// 0x6a, 0x1c, 0xe2, 0x7c
// , 0x1b, 0xbd, 0x97, 0x78, 0x70, 0xdf, 0xf1, 0x49, 0x22, 0xa6, 0x49, 0xdb,
// 0x90, 0x31, 0x63, 0x58
// , 0xc6, 0x75, 0x2f, 0xa6, 0x1b, 0xe1, 0x2e, 0x05, 0xe0, 0x7b, 0x13, 0x79,
// 0xa0, 0xfb, 0x47, 0x98
// , 0x4b, 0xfd, 0x9a, 0x5c, 0x05, 0xde, 0xac, 0xf1, 0x62, 0x3a, 0x2a, 0xb7,
// 0xec, 0xca, 0xa3, 0x43
// , 0x83, 0xd8, 0xf3, 0x2a, 0xde, 0xe4, 0xfe, 0x38, 0x02, 0x96, 0xdb, 0x95,
// 0x5a, 0x71, 0x30, 0xdd
// , 0xde, 0x9f, 0xd3, 0x07, 0x1e, 0xec, 0x5c, 0x93, 0x35, 0x1d, 0xa1, 0x65
/*---- wlan header start -----*/
0x88, /* version , type sub type */
0x02, /* Frame control flag */
0x2C, 0x00, 0x00, 0x23, 0x75, 0x55, 0x55, 0x55, /* destination */
0x00, 0x22, 0x75, 0x55, 0x55, 0x55, /* bssid */
0x08, 0x00, 0x28, 0x19, 0x02, 0x85, /* source */
0x80, 0x42, 0x00, 0x00, 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08,
0x00, /* LLC */
0x88, /* version, type and sub type */
0x08, /* Frame control flag */
0x2C, 0x00, /* Duration ID */
0x00, 0x23, 0x75, 0x55, 0x55, 0x55, /* destination */
0x08, 0x00, 0x28, 0x19, 0x02, 0x85, /* source */
0x00, 0x22, 0x75, 0x55, 0x55, 0x55, /* bssid */
0x00, 0x00, /* SC */
0x00, /* LLC */
/*---- ip header start -----*/
0x45, 0x00, 0x00, 0x54, 0x96, 0xA1, 0x00, 0x00, 0x40, 0x01, 0x57,
0xFA, /* checksum */
@ -112,6 +109,7 @@ char RawData_Ping[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
#ifdef ENABLE_DEBUG
// unsigned char g_ucDMAEnabled = 0;
void logHardwareVersion(void) {
SlVersionFull ver = {0};
@ -129,6 +127,24 @@ void logHardwareVersion(void) {
ver.ChipFwAndPhyVersion.PhyVersion[3]);
}
void printMacAddr(unsigned char *addr) {
printf("%02x:", addr[0]);
printf("%02x:", addr[1]);
printf("%02x:", addr[2]);
printf("%02x:", addr[3]);
printf("%02x:", addr[4]);
printf("%02x", addr[5]);
printf("\n");
}
void printDeviceMacAddr(void) {
unsigned char macAddr[6];
printf("### Device MAC Addr: ");
printMacAddr(macAddr);
}
#endif
/**
* @brief prepare wifi module to be operational
*
@ -138,79 +154,25 @@ void init_wifi(void) {
if (setupWifiModule() != 0) {
// loop and blink to indicate problem (also helps with debugging)
while (1) {
UtilsDelay(80 * 50);
delay(80 * 50);
gpio_toggle(LED_RED);
}
}
// light up green and disable red led
gpio_clear(LED_RED);
UtilsDelay(300000 * 80 / 3);
gpio_set(LED_GREEN);
UtilsDelay(300000 * 80 / 3);
gpio_clear(LED_GREEN);
UtilsDelay(300000 * 80 / 3);
gpio_toggle(LED_GREEN);
#ifdef ENABLE_DEBUG
logHardwareVersion();
// WifiModule t = {.fd = fd};
// test = &t;
#endif
}
#define SL_MAC_ADDRESS_GET 2
void printMacAddr(void) {
unsigned char macAddr[6];
// get mac address
getNetConfig(SL_MAC_ADDRESS_GET, NULL, 6, macAddr);
printf("MAC ADDR ");
printf("%x:", macAddr[0]);
printf("%x:", macAddr[1]);
printf("%x:", macAddr[2]);
printf("%x:", macAddr[3]);
printf("%x:", macAddr[4]);
printf("%x", macAddr[5]);
printf("\n");
}
/* sockopt */
typedef _u32 SlTime_t;
typedef _u32 SlSuseconds_t;
typedef struct SlTimeval_t {
SlTime_t tv_sec; /* Seconds */
SlSuseconds_t tv_usec; /* Microseconds */
} SlTimeval_t;
typedef struct wifi_80211_baseheader {
uint16_t fc; // frame control
uint16_t DirID; // Diration ID
uint8_t addr0[6]; // Diration ID
uint8_t addr1[6]; // Diration ID
uint8_t addr2[6]; // Diration ID
uint16_t sc; // SC
uint8_t addr3[6]; // Diration ID
} wifi_80211_baseheader;
char acBuffer[1500];
int main(void) {
uint8_t cpuid[CPUID_LEN];
// unsigned char ucVal = 0;
int16_t prepareWifi(void) {
cpuid_get(cpuid);
printf("You are running RIOT on a(n) %s board.\n", RIOT_BOARD);
init_wifi();
puts("wifi init completed !");
printMacAddr();
if (disconnectFromWifi() != 0) {
puts("[WIFI] failed to disconnect");
} else {
puts("[WIFI] disconnected");
}
unsigned char ucVal = 0;
if (setWifiPolicy(SL_POLICY_SCAN, SL_SCAN_POLICY(0)) != 0) {
puts("[WIFI] failed to set policy");
} else {
@ -218,12 +180,14 @@ int main(void) {
}
setWifiPolicy(SL_POLICY_CONNECTION, SL_CONNECTION_POLICY(0, 0, 0, 0, 0));
// deleteProfile(0xFF);
disconnectFromWifi();
if (disconnectFromWifi() != 0) {
puts("[WIFI] failed to disconnect");
} else {
puts("[WIFI] disconnected");
}
// disable DHCP
// setNetConfig(4, 1, 1, &ucVal);
setNetConfig(4, 1, 1, &ucVal);
// disable scan
if (setWifiPolicy(SL_POLICY_SCAN, SL_SCAN_POLICY(0)) != 0) {
@ -235,54 +199,106 @@ int main(void) {
uint8_t wifiPower = 0;
setWifiConfig(1, 10, 1, &wifiPower);
uint8_t filterConfig[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
// reset rx filters
setWlanFilter(1, filterConfig, sizeof(_WlanRxFilterOperationCommandBuff_t));
return 0;
}
#if RECEIVER == 1
int16_t receiveData(void) {
int16_t receiveLen = 0;
// struct SlTimeval_t timeval;
// timeval.tv_sec = 0; // Seconds
// timeval.tv_usec = 20000; // Microseconds.
// get a socket
int16_t sock = openSocket(6, 2, WLAN_CHANNEL);
if (sock < 0) {
return sock;
}
DEBUG("SOCKET OPEN: %i \n", sock);
// setSocketOptions(sock0, 1, 20, &timeval, sizeof(timeval));
while (1) {
// sendRawTraceiverData(sock0, (uint8_t *)RawData_Ping,
// sizeof(RawData_Ping), SL_RAW_RF_TX_PARAMS(13, 1, 0, 0));
receiveLen = recvRawTraceiverData(sock, acBuffer, 1470, 0);
wifi_80211_baseheader *test = (wifi_80211_baseheader *)(acBuffer + 8);
#ifdef ENABLE_DEBUG
printf("-> RECV PACKET %d bytes from MAC: ", receiveLen);
printMacAddr(test->src);
#endif
delay(4000000);
gpio_toggle(LED_ORANGE);
}
return 0;
}
#endif
#if !RECEIVER
int16_t sendData(void) {
int16_t sendLen = 0;
// get a socket
int16_t sock = openSocket(6, 2, WLAN_CHANNEL);
if (sock < 0) {
return sock;
}
DEBUG("SOCKET OPEN: %i \n", sock);
// setSocketOptions(sock0, 1, 20, &timeval, sizeof(timeval));
while (1) {
sendLen = sendRawTraceiverData(sock, (uint8_t *)RawData_Ping,
sizeof(RawData_Ping),
SL_RAW_RF_TX_PARAMS(WLAN_CHANNEL, 1, 0, 0));
#ifdef ENABLE_DEBUG
printf("<- SEND PACKET %d bytes \n", sendLen);
// printMacAddr(test->src);
#endif
delay(4000000);
gpio_toggle(LED_ORANGE);
}
return 0;
}
#endif
int main(void) {
uint8_t cpuid[CPUID_LEN];
cpuid_get(cpuid);
printf("You are running RIOT on a(n) %s board.\n", RIOT_BOARD);
init_wifi();
puts("wifi init completed !");
printf("### DEVICE MAC is: ");
printMacAddr((unsigned char *)&state.macAddr);
printDeviceMacAddr();
// configure wifi module
prepareWifi();
// connect(&apConf);
// keept the programm going
// wait for a connection
// while (state.con.connected == 0) {
// puts("waiting for connection");
// UtilsDelay(30000 * 80 / 3);
// delay(30000 * 80 / 3);
// }
puts("Connection established");
struct SlTimeval_t timeval;
timeval.tv_sec = 0; // Seconds
timeval.tv_usec = 20000; // Microseconds.
// get a socket
// SL_AF_PACKET
int16_t sock0 = openSocket(6, 2, 13);
printf("Got socket %i \n", sock0);
// char *buf = "HELLO WORLD";
setSocketOptions(sock0, 1, 20, &timeval, sizeof(timeval));
uint8_t filterConfig[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
// reset rx filters
setWlanFilter(1, filterConfig, sizeof(_WlanRxFilterOperationCommandBuff_t));
while (1) {
// sendRawTraceiverData(sock0, (uint8_t *)RawData_Ping, sizeof(RawData_Ping), SL_RAW_RF_TX_PARAMS(13, 1, 0, 0));
recvRawTraceiverData(sock0, acBuffer, 1470, 0);
// read the buffer
for(int i = 0; i < 50; i++) {
printf("%02x ", acBuffer[i]);
}
puts("");
wifi_80211_baseheader *test = (wifi_80211_baseheader *)(acBuffer + 8);
printf("GOT PACKET ");
printf("%02x:", test->addr3[0]);
printf("%02x:", test->addr3[1]);
printf("%02x:", test->addr3[2]);
printf("%02x:", test->addr3[3]);
printf("%02x:", test->addr3[4]);
printf("%02x", test->addr3[5]);
printf("\n");
UtilsDelay(4000000);
gpio_toggle(LED_GREEN);
gpio_toggle(LED_ORANGE);
gpio_toggle(LED_RED);
}
#if RECEIVER
receiveData();
#else
sendData();
#endif
return 0;
}

34
examples/wifi/proto.h
View File

@ -8,6 +8,8 @@
#define WIFI_SPI_BASE 0x44022000
#define WIFI_REG (cc3200_spi_t *)WIFI_SPI_BASE
#define SL_MAC_ADDRESS_GET 2
// ROM VERSIONS
#define ROM_VER_PG1_21 1
#define ROM_VER_PG1_32 2
@ -66,6 +68,38 @@
(!(*((uint32_t *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && \
(MATCH_WOUT_SEQ_NUM(pBuf))))
#define SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0)
#define SL_RAW_RF_TX_PARAMS_RATE_SHIFT (6)
#define SL_RAW_RF_TX_PARAMS_POWER_SHIFT (11)
#define SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15)
#define SL_RAW_RF_TX_PARAMS(chan, rate, power, preamble) \
((chan << SL_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \
(rate << SL_RAW_RF_TX_PARAMS_RATE_SHIFT) | \
(power << SL_RAW_RF_TX_PARAMS_POWER_SHIFT) | \
(preamble << SL_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT))
#define SL_POLICY_CONNECTION (0x10)
#define SL_POLICY_SCAN (0x20)
#define SL_POLICY_PM (0x30)
#define SL_POLICY_P2P (0x40)
#define VAL_2_MASK(position, value) ((1 & (value)) << (position))
#define MASK_2_VAL(position, mask) (((1 << position) & (mask)) >> (position))
#define SL_CONNECTION_POLICY(Auto, Fast, Open, anyP2P, autoSmartConfig) \
(VAL_2_MASK(0, Auto) | VAL_2_MASK(1, Fast) | VAL_2_MASK(2, Open) | \
VAL_2_MASK(3, anyP2P) | VAL_2_MASK(4, autoSmartConfig))
#define SL_SCAN_POLICY_EN(policy) (MASK_2_VAL(0, policy))
#define SL_SCAN_POLICY(Enable) (VAL_2_MASK(0, Enable))
#define SL_NORMAL_POLICY (0)
#define SL_LOW_LATENCY_POLICY (1)
#define SL_LOW_POWER_POLICY (2)
#define SL_ALWAYS_ON_POLICY (3)
#define SL_LONG_SLEEP_INTERVAL_POLICY (4)
typedef void (*SimpleLinkEventHandler)(void);
#define SimpleLinkEventHandler SimpleLinkEventHandler

69
examples/wifi/setup.c
View File

@ -9,13 +9,14 @@
#include "vendor/hw_memmap.h"
#include "vendor/hw_types.h"
#include "vendor/hw_udma.h"
#include "vendor/rom.h"
#include "vendor/rom_map.h"
// TODO: hot candidate for replacement
#include "driverlib/interrupt.h"
#include "driverlib/pin.h"
#include "driverlib/prcm.h"
#include "driverlib/rom_map.h"
#include "driverlib/spi.h"
#include "driverlib/utils.h"
// #include "driverlib/interrupt.h"
// #include "driverlib/pin.h"
// #include "driverlib/prcm.h"
// #include "driverlib/spi.h"
// #include "driverlib/utils.h"
#include "periph/spi.h"
#include <stdbool.h>
@ -48,24 +49,26 @@ uint32_t getSPIBitRate(uint8_t minorVer) {
}
int registerRxInterruptHandler(SimpleLinkEventHandler handler) {
MAP_IntRegister(INT_NWPIC, handler);
MAP_IntPrioritySet(INT_NWPIC, 0x20);
MAP_IntPendClear(INT_NWPIC);
MAP_IntEnable(INT_NWPIC);
ROM_IntRegister(INT_NWPIC, handler);
NVIC_SetPriority(INT_NWPIC, 0x20);
NVIC_ClearPendingIRQ(INT_NWPIC);
NVIC_EnableIRQ(INT_NWPIC);
// ROM_IntEnable(INT_NWPIC);
return 0;
}
void _clear_wifi_interrupt_handler(void) {
MAP_IntDisable(INT_NWPIC);
MAP_IntUnregister(INT_NWPIC);
MAP_IntPendClear(INT_NWPIC);
NVIC_DisableIRQ(INT_NWPIC);
// ROM_IntDisable(INT_NWPIC);
ROM_IntUnregister(INT_NWPIC);
NVIC_ClearPendingIRQ(INT_NWPIC);
// TODO: also clear any IO specific parts
}
void powerOffWifi(void) {
// must delay 300 usec to enable the NWP to finish all sl_stop activities
UtilsDelay(300 * 80 / 3);
delay(300 * 80 / 3);
// mask network processor interrupt interrupt
maskWifiInterrupt();
@ -76,7 +79,7 @@ void powerOffWifi(void) {
// sl_stop eco for PG1.32 devices
HWREG(0x4402E16C) |= 0x2;
UtilsDelay(800000);
delay(800000);
}
void powerOnWifi(void) {
@ -248,16 +251,17 @@ int initWifiSPI(void) {
uint32_t spiBitRate = 0;
CC3200_RomInfo *romInfo = getDeviceRomInfo();
MAP_PRCMPeripheralClkEnable(PRCM_LSPI, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// MAP_PRCMPeripheralClkEnable(PRCM_LSPI, PRCM_RUN_MODE_CLK |
// PRCM_SLP_MODE_CLK);
// Disable Chip Select
MAP_SPICSDisable(WIFI_SPI_BASE);
// // Disable Chip Select
// MAP_SPICSDisable(WIFI_SPI_BASE);
// Disable SPI Channel
MAP_SPIDisable(WIFI_SPI_BASE);
// // Disable SPI Channel
// MAP_SPIDisable(WIFI_SPI_BASE);
// reset SPI
MAP_SPIReset(WIFI_SPI_BASE);
// // reset SPI
// MAP_SPIReset(WIFI_SPI_BASE);
spiBitRate = getSPIBitRate(romInfo->minorVer);
if (spiBitRate == 0) {
@ -266,10 +270,11 @@ int initWifiSPI(void) {
// NWP master interface
// ulBase = LSPI_BASE;
MAP_SPIConfigSetExpClk(WIFI_SPI_BASE, MAP_PRCMPeripheralClockGet(PRCM_LSPI),
spiBitRate, SPI_MODE_MASTER, SPI_SUB_MODE_0,
(SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH | SPI_WL_32));
// MAP_SPIConfigSetExpClk(WIFI_SPI_BASE,
// MAP_PRCMPeripheralClockGet(PRCM_LSPI),
// spiBitRate, SPI_MODE_MASTER, SPI_SUB_MODE_0,
// (SPI_SW_CTRL_CS | SPI_4PIN_MODE | SPI_TURBO_OFF |
// SPI_CS_ACTIVEHIGH | SPI_WL_32));
// TODO: add UDMA to improve transmission performance
// if(MAP_PRCMPeripheralStatusGet(PRCM_UDMA))
@ -277,7 +282,11 @@ int initWifiSPI(void) {
// g_ucDMAEnabled = (HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0x0) ? 1 : 0;
// }
MAP_SPIEnable(WIFI_SPI_BASE);
// MAP_SPIEnable(WIFI_SPI_BASE);
spi_init(1);
spi_acquire(1, 0, SPI_SUB_MODE_0, spiBitRate);
return 0;
}
@ -296,6 +305,12 @@ int setupWifiModule(void) {
puts("failed to set wifi mode");
return -1;
}
// getDevice mac address
// get mac address
getNetConfig(SL_MAC_ADDRESS_GET, NULL, 6, (unsigned char *)&state.macAddr);
// sendPowerOnPreamble();
// if (initWifiModule() != 0) {
// puts("failed to start wifi module");

4
examples/wifi/state.h
View File

@ -15,7 +15,8 @@ typedef struct DriverRequest
{
uint8_t ID;
uint16_t Opcode;
// response description buffers
uint8_t *DescBuffer;
uint16_t DescBufferSize;
@ -35,6 +36,7 @@ typedef struct DriverState
volatile struct DriverRequest *requestQueue[REQUEST_QUEUE_SIZE];
// connection info
struct ConnectionInfo con;
unsigned char macAddr[6];
} DriverState;
extern DriverState state;

1
examples/wifi/utils.h
View File

@ -4,6 +4,7 @@
#include "proto.h"
#define alignDataLen(len) ((len) + 3) & (~3)
extern void __attribute__((naked)) delay(unsigned long count);
void printChars(char *str, uint16_t len);
void maskWifiInterrupt(void);
void unmaskWifiInterrupt(void);