From ea4e5ce3aa266a175c5502d99e7e90e8b7e6d02f Mon Sep 17 00:00:00 2001 From: Wlad Meixner Date: Thu, 25 Jul 2019 10:45:00 +0200 Subject: [PATCH] CC3200: cleanup & add documentation --- cpu/cc3200/include/cc3200.h | 8 ----- cpu/cc3200/include/cc3200_gpio.h | 26 ++++++++-------- cpu/cc3200/periph/gpio.c | 51 ++++++++++++++++++-------------- 3 files changed, 41 insertions(+), 44 deletions(-) diff --git a/cpu/cc3200/include/cc3200.h b/cpu/cc3200/include/cc3200.h index b7d8d9192..4efd0f8bb 100644 --- a/cpu/cc3200/include/cc3200.h +++ b/cpu/cc3200/include/cc3200.h @@ -108,16 +108,8 @@ typedef enum IRQn { 0 /**< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 0 /**< CC3200 has not FPU */ -#define SW_TIMERS_EXAUSTED 111 - #define CC3200_VTOR_ALIGN 1024 /**< CC3200 Vector Table alignment */ -/** @addtogroup cpu_specific_Peripheral_memory_map - * @{ - */ -#define PERIPH_BASE 0x40000000U -/** @} */ - #ifdef __cplusplus } /* end extern "C" */ #endif diff --git a/cpu/cc3200/include/cc3200_gpio.h b/cpu/cc3200/include/cc3200_gpio.h index 97da0ad11..c16621848 100644 --- a/cpu/cc3200/include/cc3200_gpio.h +++ b/cpu/cc3200/include/cc3200_gpio.h @@ -70,12 +70,12 @@ typedef uint32_t gpio_t; */ #define HAVE_GPIO_MODE_T typedef enum { - GPIO_IN = 0x00000000, /**< input, no pull */ - GPIO_OUT = 0x00000001, /**< output */ - GPIO_OD = 0x00000002, /**< open drain */ - GPIO_OD_PU = 0x00000106, /**< open drain pull-up */ - GPIO_IN_PU = 0x00000107, /**< input, pull-up */ - GPIO_IN_PD = 0x00000208, /**< input, pull-down */ + GPIO_IN = 0x00000000, /**< input, no pull */ + GPIO_OUT = 0x00000001, /**< output */ + GPIO_OD = 0x00000002, /**< open drain */ + GPIO_OD_PU = 0x00000106, /**< open drain pull-up */ + GPIO_IN_PU = 0x00000107, /**< input, pull-up */ + GPIO_IN_PD = 0x00000208, /**< input, pull-down */ } gpio_mode_t; /** @} */ @@ -86,12 +86,12 @@ typedef enum { */ #define HAVE_GPIO_FLANK_T typedef enum { - GPIO_FALLING = 0, /**< emit interrupt on falling flank */ - GPIO_BOTH = 1, /**< emit interrupt on both flanks */ - GPIO_LOW = 2, /**< emit interrupt on low level */ - GPIO_RISING = 4, /**< emit interrupt on rising flank */ - GPIO_NONE = 5, /**< no interrupt */ - GPIO_HIGH = 6 /**< emit interrupt on low level */ + GPIO_FALLING = 0, /**< emit interrupt on falling flank */ + GPIO_BOTH = 1, /**< emit interrupt on both flanks */ + GPIO_LOW = 2, /**< emit interrupt on low level */ + GPIO_RISING = 4, /**< emit interrupt on rising flank */ + GPIO_NONE = 5, /**< no interrupt */ + GPIO_HIGH = 6 /**< emit interrupt on low level */ } gpio_flank_t; /** @} */ @@ -133,4 +133,4 @@ typedef struct cc3200_gpio_t { #endif /* CC3200_GPIO_H */ -/** @} */ \ No newline at end of file +/** @} */ diff --git a/cpu/cc3200/periph/gpio.c b/cpu/cc3200/periph/gpio.c index 32433d5ab..e4c7eafe2 100644 --- a/cpu/cc3200/periph/gpio.c +++ b/cpu/cc3200/periph/gpio.c @@ -35,17 +35,26 @@ static gpio_isr_ctx_t isr_ctx[4][8]; #endif /* MODULE_PERIPH_GPIO_IRQ */ -#define GPIO_DIR_MASK 0x00000001 -#define PIN_MODE_GPIO 0x00000000 -#define GPIO_PORT_MASK (0xfffff000) /**< bit mask for GPIO port addr */ -#define NOT_A_PORT 0 -#define NOT_A_PIN 0 -#define NOT_A_GPIO 66 -#define PAD_MODE_MASK 0x0000000F -#define PAD_STRENGTH_MASK 0x000000E0 -#define PAD_TYPE_MASK 0x00000310 +#define GPIO_PINS_PER_PORT 8 /**< Number of pins per port */ +#define GPIO_DIR_MASK 0x00000001 /**< GPIO direction configuration mask */ +#define PIN_MODE_GPIO \ + 0x00000000 /**< GPIO Pin type value used to configure pin to GPIO */ +#define PAD_MODE_MASK 0x0000000F /**< GPIO mask for setting pin mode */ +#define PAD_STRENGTH_MASK \ + 0x000000E0 /**< GPIO mask for setting pin strength \ + */ +#define PAD_TYPE_MASK \ + 0x00000310 /**< GPIO mask for setting pin type e.g. PULL \ + */ #define PAD_CONFIG_BASE ((OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0)) +/** + * @brief get hardware configuration register for a pin + * + */ +#define PAD_CONFIG_REG(pin) \ + (*((volatile unsigned long *)((gpio_pin << 2) + PAD_CONFIG_BASE))) + /** * @brief gpio base addresses * @@ -150,14 +159,13 @@ void gpio_init_af(gpio_t dev, uint32_t strength, uint32_t type) /* now only replecate behaviour. */ /* enable input */ - HWREG(0x4402E144) &= ~((0x80 << gpio_pin) & (0x1E << 8)); + HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= + ~((0x80 << gpio_pin) & (0x1E << 8)); - /* compute pin register */ - unsigned long regAddr = (gpio_pin << 2) + PAD_CONFIG_BASE; - - /* write config */ - HWREG(regAddr) = ((HWREG(regAddr) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | - (strength | type)); + /* write config to hardware register referred by TI as PAD */ + PAD_CONFIG_REG(gpio_pin) = + ((PAD_CONFIG_REG(gpio_pin) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | + (strength | type)); } void gpio_pin_mode_set(gpio_t dev, uint32_t mode) @@ -166,11 +174,9 @@ void gpio_pin_mode_set(gpio_t dev, uint32_t mode) uint8_t pin = gpio_pin_num(dev); uint8_t gpio_pin = pin_to_gpio_num[pin]; - /* compute pin register */ - unsigned long regAddr = (gpio_pin << 2) + PAD_CONFIG_BASE; - /* set mode */ - HWREG(regAddr) = (((HWREG(regAddr) & ~PAD_MODE_MASK) | mode) & ~(3 << 10)); + PAD_CONFIG_REG(gpio_pin) = + (((PAD_CONFIG_REG(gpio_pin) & ~PAD_MODE_MASK) | mode) & ~(3 << 10)); } int gpio_init(gpio_t dev, gpio_mode_t mode) @@ -333,7 +339,7 @@ void gpio_write(gpio_t dev, int value) unsigned char ipin = gpio_pin_mask(dev); unsigned long portAddr = gpio_pin_to_port(port); /* write to pin at portBase + pinOffset */ - HWREG(portAddr + (0x00000000 + (ipin << 2))) = + HWREG(portAddr + (ipin << 2)) = _gpio_pin_value_mask(pin_to_gpio_num[gpio_pin_num(dev)], value); } @@ -351,8 +357,7 @@ int gpio_read(gpio_t dev) /* read from pin at portBase + pinOffset */ /* cast value to int {0, 1} */ - return (HWREG(portAddr + (0x00000000 + (ipin << 2))) ? GPIO_VALUE_HIGH : - GPIO_VALUE_LOW); + return (HWREG(portAddr + (ipin << 2)) ? GPIO_VALUE_HIGH : GPIO_VALUE_LOW); } /**