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121 lines
4.5 KiB
C
121 lines
4.5 KiB
C
/*
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* Copyright (C) 2019 Ludwig Maximilian Universität
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc3200
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* @{
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*
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* @file
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* @brief Interrupt vector definitions
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*
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* @author Wladislaw Meixner <wladislaw.meixner@campus.lmu.de>
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*
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* @{
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*/
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#include "board.h"
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#include "cpu.h"
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#include "vectors_cortexm.h"
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#include <stdint.h>
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void)
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{
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dummy_handler_default();
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}
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/* CC3200 specific interrupt vectors */
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WEAK_DEFAULT void isr_gpio_porta0(void);
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WEAK_DEFAULT void isr_gpio_porta1(void);
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WEAK_DEFAULT void isr_gpio_porta2(void);
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WEAK_DEFAULT void isr_gpio_porta3(void);
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WEAK_DEFAULT void isr_uart0(void);
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WEAK_DEFAULT void isr_uart1(void);
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WEAK_DEFAULT void isr_i2c0(void);
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WEAK_DEFAULT void isr_adc0_seq0(void);
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WEAK_DEFAULT void isr_adc0_seq1(void);
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WEAK_DEFAULT void isr_adc0_seq2(void);
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WEAK_DEFAULT void isr_adc0_seq3(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_timer0_ch_a(void);
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WEAK_DEFAULT void isr_timer0_ch_b(void);
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WEAK_DEFAULT void isr_timer1_ch_a(void);
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WEAK_DEFAULT void isr_timer1_ch_b(void);
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WEAK_DEFAULT void isr_timer2_ch_a(void);
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WEAK_DEFAULT void isr_timer2_ch_b(void);
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WEAK_DEFAULT void isr_timer3_ch_a(void);
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WEAK_DEFAULT void isr_timer3_ch_b(void);
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WEAK_DEFAULT void isr_flashctl(void);
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WEAK_DEFAULT void isr_udma_sw(void);
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WEAK_DEFAULT void isr_udma_error(void);
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WEAK_DEFAULT void isr_sha(void);
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WEAK_DEFAULT void isr_aes(void);
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WEAK_DEFAULT void isr_des(void);
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WEAK_DEFAULT void isr_sdhost(void);
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WEAK_DEFAULT void isr_i2s(void);
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WEAK_DEFAULT void isr_camera(void);
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WEAK_DEFAULT void isr_shared_spi(void);
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WEAK_DEFAULT void isr_generic_spi(void);
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WEAK_DEFAULT void isr_link_spi(void);
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WEAK_DEFAULT void isr_nwp(void);
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WEAK_DEFAULT void isr_prcm(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1)
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const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[0] = isr_gpio_porta0, /* 16 GPIO Port A */
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[1] = isr_gpio_porta1, /* 17 GPIO Port B */
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[2] = isr_gpio_porta2, /* 18 GPIO Port C */
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[3] = isr_gpio_porta3, /* 19 GPIO Port D */
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/* 20 Reserved */
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[5] = isr_uart0, /* 21 UART0 Rx and Tx */
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[6] = isr_uart1, /* 22 UART1 Rx and Tx */
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/* 23 Reserved */
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[8] = isr_i2c0, /* 24 I2C0 Master and Slave */
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/* 25 - 29 Reserved */
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[14] = isr_adc0_seq0, /* 30 ADC 0 Sequence 0 */
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[15] = isr_adc0_seq1, /* 31 ADC 0 Sequence 1 */
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[16] = isr_adc0_seq2, /* 32 ADC 0 Sequence 2 */
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[17] = isr_adc0_seq3, /* 33 ADC 0 Sequence 3 */
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[18] = isr_wdt, /* 34 Watchdog timer */
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[19] = isr_timer0_ch_a, /* 35 Timer 0 subtimer A */
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[20] = isr_timer0_ch_b, /* 36 Timer 0 subtimer B */
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[21] = isr_timer1_ch_a, /* 37 Timer 1 subtimer A */
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[22] = isr_timer1_ch_b, /* 38 Timer 1 subtimer B */
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[23] = isr_timer2_ch_a, /* 39 Timer 2 subtimer A */
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[24] = isr_timer2_ch_b, /* 40 Timer 2 subtimer B */
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/* 41 - 44 Reserved */
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[29] = isr_flashctl, /* 45 Flash */
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/* 46 - 50 Reserved */
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[35] = isr_timer3_ch_a, /* 51 Timer 3 subtimer B */
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[36] = isr_timer3_ch_b, /* 52 Timer 3 subtimer B */
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/* 53 - 61 Reserved */
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[46] = isr_udma_sw, /* 62 uDMA Software Transfer */
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[47] = isr_udma_error, /* 63 uDMA Error */
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/* 64 - 163 Reserved */
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[148] = isr_sha, /* 164 SHA */
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/* 165 - 166 Reserved */
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[151] = isr_aes, /* 167 AES */
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/* 168 Reserved */
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[153] = isr_des, /* 169 DES */
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/* Reserved */
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[159] = isr_sdhost, /* 175 SDHost */
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/* 176 Reserved */
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[161] = isr_i2s, /* 177 I2S */
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/* 178 Reserved */
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[163] = isr_camera, /* 179 Camera */
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/* 181 - 186 Reserved */
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[171] = isr_nwp, /* 187 NWP to APPS Interrupt */
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[172] = isr_prcm, /* 188 Power, Reset and Clock module */
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/* 189 - 190 Reserved */
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[175] = isr_shared_spi, /* 191 Shared SPI interrupt (for SFLASH) */
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[176] = isr_generic_spi, /* 192 SPI */
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[177] = isr_link_spi, /* 193 Link SPI (APPS to NWP) */
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};
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