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temporary test setup

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This commit is contained in:
Wlad Meixner 2019-10-16 19:29:22 +02:00
parent 777cdbf4ad
commit a99210cea8
13 changed files with 528 additions and 201 deletions
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6
cpu/cc3200/include/periph_cpu.h
View File

@ -48,7 +48,7 @@ extern "C" {
/**
* @brief Length of the CPU_ID in octets
*/
#define CPUID_LEN (4U)
#define CPUID_LEN (6U)
/**
* @brief holds the current hibernation state of the MCU. READONLY and reading
@ -84,8 +84,8 @@ typedef struct {
* (without gaps) starting from GPT0, i.e. if multiple timers are enabled.
*/
typedef struct {
uint8_t chn; /**< number of channels */
uint8_t cfg; /**< timer config word */
uint8_t chn; /**< number of channels */
uint8_t cfg; /**< timer config word */
} timer_conf_t;
/**

18
cpu/cc3200/periph/cpuid.c
View File

@ -23,7 +23,23 @@
#include "cpu.h"
#include "periph/cpuid.h"
typedef struct {
unsigned char rev : 4;
unsigned char part_no_2 : 8;
unsigned char part_no_1 : 4;
unsigned char con : 4;
unsigned char var : 4;
unsigned char imp : 8;
} cpuid_t;
void cpuid_get(void *id)
{
memcpy(id, CPUID_ADDR, CPUID_LEN);
cpuid_t *cpuid = ((cpuid_t *)CPUID_ADDR);
unsigned char *_id = id;
_id[0] = cpuid->rev;
_id[1] = cpuid->part_no_1;
_id[2] = cpuid->part_no_2;
_id[3] = cpuid->con;
_id[4] = cpuid->var;
_id[5] = cpuid->imp;
}

2
cpu/cc3200/periph/spi.c
View File

@ -211,7 +211,7 @@ void spi_release(spi_t bus)
}
/* disable spi */
spi(bus)->ch0_ctrl &= ~MCSPI_CH0CTRL_EN;
// spi(bus)->ch0_ctrl &= ~MCSPI_CH0CTRL_EN;
mutex_unlock(&locks[bus]);
}

167
cpu/cc3200/periph/timer.c
View File

@ -93,6 +93,69 @@ static inline cc3200_timer_t *timer(tim_t num)
return (cc3200_timer_t *)(TIMERA0_BASE + (num << 12));
}
/**
* @brief timer interrupt handler
*
* @param[in] dev GPT instance number
*/
static void timer_irq_handler(tim_t tim, int channel)
{
// DEBUG("%s(%u,%d, %u)\n", __FUNCTION__, tim, channel, timer_read(tim));
assert(tim < TIMER_NUMOF);
assert(channel < (int)timer_config[tim].chn);
uint32_t mis;
/* Latch the active interrupt flags */
mis = timer(tim)->masked_intr & chn_isr_cfg[channel].mask;
/* Clear the latched interrupt flags */
timer(tim)->intr_clear = mis;
// DEBUG("EXECUTE CALLBACK\n");
if (mis & chn_isr_cfg[channel].flag) {
// DEBUG("[OK]EXECUTE CALLBACK\n");
/* Disable further match interrupts for this timer/channel */
timer(tim)->masked_intr &= ~chn_isr_cfg[channel].flag;
/* Invoke the callback function */
isr_ctx[tim].cb(isr_ctx[tim].arg, channel);
// DEBUG("[DONE]EXECUTE CALLBACK\n");
}
cortexm_isr_end();
}
void isr_timer0_ch_a(void)
{
timer_irq_handler(0, 0);
};
void isr_timer0_ch_b(void)
{
timer_irq_handler(0, 1);
};
void isr_timer1_ch_a(void)
{
timer_irq_handler(1, 0);
};
void isr_timer1_ch_b(void)
{
timer_irq_handler(1, 1);
};
void isr_timer2_ch_a(void)
{
timer_irq_handler(2, 0);
};
void isr_timer2_ch_b(void)
{
timer_irq_handler(2, 1);
};
void isr_timer3_ch_a(void)
{
timer_irq_handler(3, 0);
};
void isr_timer3_ch_b(void)
{
timer_irq_handler(3, 1);
};
/**
* @brief returns the timer peripheral register used to enable or disable
* hardware peripheral.
@ -166,19 +229,31 @@ int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
return -1;
}
t->conf = timer_config[tim].cfg;
t->conf = timer_config[tim].cfg; // | TIMER_CFG_A_PERIODIC_UP >> 24;
t->ctrl &= TAEN;
t->timer_a_mode = chan_mode;
t->timer_a_mode = chan_mode & 255;
if (timer_config[tim].chn > 1) {
t->timer_b_mode = chan_mode;
t->timer_b_mode = chan_mode & 255;
t->prescale_b = prescaler;
t->interval_load_b = LOAD_VALUE;
/* Enable the timer: */
t->ctrl &= TBEN;
}
_irq_enable(tim);
ROM_TimerConfigure((uint32_t)timer(tim), 0x04000000 | TIMER_CFG_A_PERIODIC);
ROM_TimerPrescaleSet((uint32_t)timer(tim), TIMER_A, 79);
ROM_TimerIntRegister((uint32_t)timer(tim), TIMER_A, isr_timer0_ch_a);
// ROM_TimerControlStall((uint32_t)timer(tim), TIMER_A, true);
ROM_IntPriorityGroupingSet(3);
ROM_IntPrioritySet(INT_TIMERA0A, 0xFF);
// ROM_TimerLoadSet((uint32_t)timer(tim), TIMER_A, 5000);
ROM_TimerIntEnable((uint32_t)timer(tim), TIMER_CAPA_MATCH);
ROM_TimerEnable((uint32_t)timer(tim), TIMER_A);
// _irq_enable(tim);
return 0;
}
@ -186,16 +261,16 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
{
DEBUG("timer_set_absolute(%u, %u, %u)\n", tim, channel, value);
if (tim >= TIMER_NUMOF || channel >= (int)timer_config[tim].chn) {
return -1;
}
// if (tim >= TIMER_NUMOF || channel >= (int)timer_config[tim].chn) {
// return -1;
// }
/* clear any pending match interrupts */
timer(tim)->intr_clear = chn_isr_cfg[channel].flag;
if (channel == 0) {
timer(tim)->match_a =
(timer_config[tim].cfg == TIMER_CFG_32_BIT_TIMER) ?
value :
(LOAD_VALUE - value);
ROM_TimerMatchSet((uint32_t)timer(tim), TIMER_A, (uint32_t)timer(tim));
// printf("timer_set_absolute(%u, %u)\n", (uint16_t)timer(tim)->val_a,
// value);
} else {
timer(tim)->match_b =
(timer_config[tim].cfg == TIMER_CFG_32_BIT_TIMER) ?
@ -224,12 +299,15 @@ unsigned int timer_read(tim_t tim)
if (tim >= TIMER_NUMOF) {
return 0;
}
// while (true) {
// DEBUG("a= %d | b= %ld \n", (uint16_t)timer(tim)->val_a,
// (uint32_t)timer(tim)->val_b);
// }
if (timer_config[tim].cfg == TIMER_CFG_32_BIT_TIMER) {
return timer(tim)->val_a;
} else {
unsigned int val = LOAD_VALUE - (timer(tim)->val_a & 0xFFFF);
return val;
return (uint16_t)(timer(tim)->val_a);
}
}
@ -254,66 +332,3 @@ void timer_stop(tim_t tim)
timer(tim)->ctrl = 0;
}
}
/**
* @brief timer interrupt handler
*
* @param[in] dev GPT instance number
*/
static void timer_irq_handler(tim_t tim, int channel)
{
DEBUG("%s(%u,%d, %u)\n", __FUNCTION__, tim, channel, timer_read(tim));
assert(tim < TIMER_NUMOF);
assert(channel < (int)timer_config[tim].chn);
uint32_t mis;
/* Latch the active interrupt flags */
mis = timer(tim)->masked_intr & chn_isr_cfg[channel].mask;
/* Clear the latched interrupt flags */
timer(tim)->intr_clear = mis;
DEBUG("EXECUTE CALLBACK\n");
if (mis & chn_isr_cfg[channel].flag) {
DEBUG("[OK]EXECUTE CALLBACK\n");
/* Disable further match interrupts for this timer/channel */
timer(tim)->masked_intr &= ~chn_isr_cfg[channel].flag;
/* Invoke the callback function */
isr_ctx[tim].cb(isr_ctx[tim].arg, channel);
DEBUG("[DONE]EXECUTE CALLBACK\n");
}
cortexm_isr_end();
}
void isr_timer0_ch_a(void)
{
timer_irq_handler(0, 0);
};
void isr_timer0_ch_b(void)
{
timer_irq_handler(0, 1);
};
void isr_timer1_ch_a(void)
{
timer_irq_handler(1, 0);
};
void isr_timer1_ch_b(void)
{
timer_irq_handler(1, 1);
};
void isr_timer2_ch_a(void)
{
timer_irq_handler(2, 0);
};
void isr_timer2_ch_b(void)
{
timer_irq_handler(2, 1);
};
void isr_timer3_ch_a(void)
{
timer_irq_handler(3, 0);
};
void isr_timer3_ch_b(void)
{
timer_irq_handler(3, 1);
};

18
cpu/cc3200/vectors.c
View File

@ -18,8 +18,8 @@
* @{
*/
#include "cpu.h"
#include "board.h"
#include "cpu.h"
#include "vectors_cortexm.h"
#include <stdint.h>
@ -84,17 +84,17 @@ const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[16] = isr_adc0_seq2, /* 32 ADC 0 Sequence 2 */
[17] = isr_adc0_seq3, /* 33 ADC 0 Sequence 3 */
[18] = isr_wdt, /* 34 Watchdog timer */
[19] = isr_timer0_ch_a, /* 35 Timer 0 subtimer A */
[20] = isr_timer0_ch_b, /* 36 Timer 0 subtimer B */
[21] = isr_timer1_ch_a, /* 37 Timer 1 subtimer A */
[22] = isr_timer1_ch_b, /* 38 Timer 1 subtimer B */
[23] = isr_timer2_ch_a, /* 39 Timer 2 subtimer A */
[24] = isr_timer2_ch_b, /* 40 Timer 2 subtimer B */
[19] = isr_timer0_ch_a, /* 35 Timer 0 subtimer A */
[20] = isr_timer0_ch_b, /* 36 Timer 0 subtimer B */
[21] = isr_timer1_ch_a, /* 37 Timer 1 subtimer A */
[22] = isr_timer1_ch_b, /* 38 Timer 1 subtimer B */
[23] = isr_timer2_ch_a, /* 39 Timer 2 subtimer A */
[24] = isr_timer2_ch_b, /* 40 Timer 2 subtimer B */
/* 41 - 44 Reserved */
[29] = isr_flashctl, /* 45 Flash */
/* 46 - 50 Reserved */
[35] = isr_timer3_ch_a, /* 51 Timer 3 subtimer B */
[36] = isr_timer3_ch_b, /* 52 Timer 3 subtimer B */
[35] = isr_timer3_ch_a, /* 51 Timer 3 subtimer B */
[36] = isr_timer3_ch_b, /* 52 Timer 3 subtimer B */
/* 53 - 61 Reserved */
[46] = isr_udma_sw, /* 62 uDMA Software Transfer */
[47] = isr_udma_error, /* 63 uDMA Error */

2
cpu/native/include/periph_cpu.h
View File

@ -29,7 +29,7 @@ extern "C" {
* @brief Length of the CPU_ID in octets
*/
#ifndef CPUID_LEN
#define CPUID_LEN (4U)
#define CPUID_LEN (5U)
#endif
/**

54
drivers/cc3100/cc3100_internal.c
View File

@ -10,9 +10,9 @@
#include "cc3100.h"
#include "include/cc3100_internal.h"
#include "include/cc3100_netdev.h"
#include "include/cc3100_nwp_com.h"
#include "include/cc3100_protocol.h"
#include "include/cc3100_netdev.h"
#include <stdbool.h>
#include <stddef.h>
@ -61,19 +61,12 @@ void printMacAddr(unsigned char *addr)
#define WAKENWP_WAKEREQ \
(APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST)
// TODO: finetune this shared buffer and maybe move it to dev
static uint8_t sharedBuffer[512];
/* static header buffer */
static cc3100_nwp_resp_header_t _cmd_header = {};
/**
* @brief Transmission sequence number used for NWP <-> CPU sync
*
*/
static uint32_t TxSeqNum = 0;
const cc3100_nwp_sync_pattern_t CPU_TO_NWP_SYNC_PATTERN =
CPU_TO_NET_CHIP_SYNC_PATTERN;
const cc3100_nwp_sync_pattern_t CPU_TO_NWP_CNYS_PATTERN =
@ -87,14 +80,12 @@ void sliceFirstInBuffer(uint8_t *buf, int len);
void cc3100_add_to_drv_queue(volatile cc31xx_nwp_req_t *req);
uint8_t cc3100_remove_from_drv_queue(volatile cc31xx_nwp_req_t *req);
/**
* @brief cc3100_nwp_rx_handler is the default RX handlers for the NWP
*
*/
void cc3100_nwp_rx_handler(void)
{
DEBUG("%s()\n", __FUNCTION__);
/* reset header buffer values */
@ -257,7 +248,7 @@ int cc3100_read_from_nwp(cc3100_t *dev, void *buf, int len)
{
DEBUG("%s()\n", __FUNCTION__);
// spi_transfer_bytes(dev->params.spi, SPI_CS_UNDEF, false, NULL, buf, len);
spi_transfer_bytes(1, SPI_CS_UNDEF, false, NULL, buf, len);
spi_transfer_bytes(1, SPI_CS_UNDEF, false, NULL, buf, ((len) + 3) & (~3));
return len;
}
@ -272,7 +263,7 @@ int cc31xx_send_to_nwp(cc3100_t *dev, const void *buf, int len)
{
DEBUG("%s()\n", __FUNCTION__);
// spi_transfer_bytes(dev->params.spi, SPI_CS_UNDEF, false, buf, NULL, len);
spi_transfer_bytes(1, SPI_CS_UNDEF, false, buf, NULL, len);
spi_transfer_bytes(1, SPI_CS_UNDEF, false, buf, NULL, ((len) + 3) & (~3));
return len;
}
@ -328,10 +319,11 @@ void cc3100_cmd_handler(cc3100_t *dev, cc3100_nwp_resp_header_t *header)
cc3100_remove_from_drv_queue(_nwp_com.queue[i]);
}
spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
// spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
/* when we have a request read the buffer to the request */
if (req != NULL) {
DEBUG("[cc31xx] drv requests found \n");
int16_t remainder = header->GenHeader.Len - req->desc_len;
if (remainder < 0) {
remainder = 0;
@ -358,12 +350,13 @@ void cc3100_cmd_handler(cc3100_t *dev, cc3100_nwp_resp_header_t *header)
if (remainder > 0) {
cc3100_read_from_nwp(dev, sharedBuffer, remainder);
}
} else {
/* otherwise read everything into shared buffer */
cc3100_read_from_nwp(dev, sharedBuffer, header->GenHeader.Len);
}
// else {
// /* otherwise read everything into shared buffer */
// cc3100_read_from_nwp(dev, sharedBuffer, header->GenHeader.Len);
// }
spi_release(1);
// spi_release(1);
unmask_nwp_rx_irqn();
}
@ -434,7 +427,7 @@ int cc31xx_read_cmd_header(cc3100_t *dev, cc3100_nwp_resp_header_t *buf)
/* acquire spi */
// spi_acquire(dev->params.spi, SPI_CS_UNDEF, SPI_SUB_MODE_0,
// dev->params.spi);
spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
// spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
/* write sync pattern to indicate read start */
cc31xx_send_to_nwp(dev, &CPU_TO_NWP_CNYS_PATTERN.Short, sizeof(uint32_t));
@ -450,12 +443,17 @@ int cc31xx_read_cmd_header(cc3100_t *dev, cc3100_nwp_resp_header_t *buf)
if (0 == (SyncCnt % (uint32_t)4)) {
cc3100_read_from_nwp(dev, &buf[4], 4);
}
ROM_UtilsDelay(100);
/* move content of buffer by one byte to the left */
sliceFirstInBuffer((uint8_t *)buf, 8);
/* increase sync counter to keep track of sliced of bytes */
SyncCnt++;
/* fail transmission after no response */
if (SyncCnt == 40) {
return 0;
}
}
SyncCnt %= 4;
@ -486,7 +484,7 @@ int cc31xx_read_cmd_header(cc3100_t *dev, cc3100_nwp_resp_header_t *buf)
cc3100_read_from_nwp(dev, buf,
(uint8_t)((SyncCnt > 0) ? (4 - SyncCnt) : 0));
spi_release(1);
// spi_release(1);
return 0;
}
@ -530,7 +528,7 @@ uint8_t cc31xx_send_nwp_cmd(cc3100_t *dev, cc31xx_nwp_msg_t *msg,
/* aquire SPI device */
// spi_acquire(dev->params.spi, SPI_CS_UNDEF, SPI_SUB_MODE_0,
// dev->params.spi);
spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
// spi_acquire(1, SPI_CS_UNDEF, SPI_SUB_MODE_0, SPI_CLK_20MHZ);
DEBUG("\033[0;34m[WIFI]\033[0m SEND CMD: \033[1;33m%x\033[0m\n",
msg->opcode);
@ -544,7 +542,9 @@ uint8_t cc31xx_send_nwp_cmd(cc3100_t *dev, cc31xx_nwp_msg_t *msg,
msg->desc_len);
cc3100_nwp_header_t header = { .opcode = msg->opcode, .len = desc_len };
// add request to the request queue
volatile cc31xx_nwp_req_t req = { .opcode = msg->opcode - 0x8000,
volatile cc31xx_nwp_req_t req = { .opcode = msg->resp_opcode != 0 ?
msg->resp_opcode :
msg->opcode - 0x8000,
.wait = true,
.desc_len = res->res_len,
.desc_buf = res->data };
@ -572,24 +572,26 @@ uint8_t cc31xx_send_nwp_cmd(cc3100_t *dev, cc31xx_nwp_msg_t *msg,
/* if a payload header is provided send it */
if (msg->payload_hdr_len > 0) {
DEBUG("SEND HEADER\n");
/* send command descriptions */
cc31xx_send_to_nwp(dev, msg->payload_hdr_buf,
alignDataLen(msg->payload_hdr_len));
}
/* send payload if provided */
if (msg->payload_len > 0) {
if (msg->payload_buf != NULL && msg->payload_len > 0) {
DEBUG("SEND PAYLOAD\n");
cc31xx_send_to_nwp(dev, msg->payload_buf,
alignDataLen(msg->payload_len));
}
/* release SPI device */
// spi_release(dev->params.spi);
spi_release(1);
// spi_release(1);
// wait for message response (rxHandler will copy the value to the res
// buffer)
// TODO: handle timeouts
while (req.wait) {
while (res != NULL && req.wait) {
thread_yield();
}
return 0;
@ -651,7 +653,7 @@ uint16_t _nwp_setup(cc3100_t *dev)
}
/* open RAW socket */
int16_t sock = _nwp_sock_create(dev, SL_AF_RF, SL_SOCK_RAW, WIFI_CHANNEL);
int16_t sock = _nwp_sock_create(dev, SL_AF_RF, SL_SOCK_RAW, WIFI_CHANNEL);
if (sock < 0) {
DEBUG("[cc31xx] failed to open raw socket\n");
}

260
drivers/cc3100/cc3100_netdev.c
View File

@ -3,26 +3,67 @@
#include <stdbool.h>
#include <string.h>
#ifdef CPU_CC3200
#include "vendor/rom.h"
#endif
#include "fmt.h"
#include "irq_handler.h"
#include "net/gnrc.h"
#include "net/gnrc/netif.h"
#include "net/netdev.h"
#include "net/netopt.h"
#include "irq_handler.h"
#include "thread.h"
#include "xtimer.h"
#include "cc3100.h"
#include "include/cc3100_internal.h"
#include "include/cc3100_netdev.h"
#include "include/cc3100_nwp_com.h"
#include "include/cc3100_registers.h"
#include "periph/spi.h"
#include "net/netdev/ieee80211.h"
#define ENABLE_DEBUG (1)
#include "debug.h"
#if defined(MODULE_OD) && ENABLE_DEBUG
#include "od.h"
#endif
char RawData_Ping[] = {
/*---- wlan header start -----*/
0x88, /* version , type sub type */
0x02, /* Frame control flag */
0x2C, 0x00, /* Duration ID */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* destination */
0x22, 0x33, 0x44, 0x55, 0x66, 0x77, /* bssid */
0xe0, 0xe5, 0xcf, 0xbc, 0x71, 0xd0, /* source */
// 0x80, 0x42, 0x00, 0x00, 0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08,
// 0x00, /* LLC */
// /*---- ip header start -----*/
// 0x08, 0x00,
0x63, 0x63, 0x33, 0x31, 0x78, 0x78, 0x20, 0x64, 0x61, 0x74, 0x61, 0x20,
0x74, 0x65, 0x73, 0x74, 0x20, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69,
0x73, 0x73, 0x69, 0x6f, 0x6e
// 0x54, 0x65, 0x73, 0x74, 0x20, 0x74, 0x72, 0x61, 0x6e, 0x73, 0x6d, 0x69,
// 0x73, 0x73, 0x69, 0x6f, 0x6e
// 0x45, 0x00, 0x00, 0x54, 0x96, 0xA1, 0x00, 0x00, 0x40, 0x01, 0x57,
// 0xFA, /* checksum */
// 0xff, 0xff, 0xff, 0xff, /* src ip */
// 0xc0, 0xa8, 0x01, 0x02, /* dest ip */
/* payload - ping/icmp */
// 0x08, 0x00, 0xA5, 0x51, 0x5E, 0x18, 0x00, 0x00, 0x41, 0x08, 0xBB, 0x8D,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
// 0x00, 0x00, 0x00, 0x00, .....
};
static int _send(netdev_t *netdev, const iolist_t *iolist);
static int _recv(netdev_t *netdev, void *buf, size_t len, void *info);
static int _init(netdev_t *netdev);
@ -30,42 +71,13 @@ static void _isr(netdev_t *netdev);
static int _get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len);
static int _set(netdev_t *netdev, netopt_t opt, const void *val, size_t len);
char RawData_Ping[] = {
/*---- wlan header start -----*/
0x88, /* version , type sub type */
0x02, /* Frame control flag */
0x2C, 0x00,
0x00, 0x23, 0x75, 0x55,0x55, 0x55, /* destination */
0x00, 0x22, 0x75, 0x55,0x55, 0x55, /* bssid */
0x08, 0x00, 0x28, 0x19,0x02, 0x85, /* source */
0x80, 0x42, 0x00, 0x00,
0xAA, 0xAA, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, /* LLC */
/*---- ip header start -----*/
0x45, 0x00, 0x00, 0x54, 0x96, 0xA1, 0x00, 0x00, 0x40, 0x01,
0x57, 0xFA, /* checksum */
0xc0, 0xa8, 0x01, 0x64, /* src ip */
0xc0, 0xa8, 0x01, 0x02, /* dest ip */
/* payload - ping/icmp */
0x08, 0x00, 0xA5, 0x51,
0x5E, 0x18, 0x00, 0x00, 0x41, 0x08, 0xBB, 0x8D, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static irq_event_t _irq_nwp_event = IRQ_EVENT_INIT;
extern uint8_t _cc31xx_isr_state;
void _irq_event(void *args) {
void _irq_event(void *args)
{
(void)args;
mask_nwp_rx_irqn();
_irq_nwp_event.isr(_irq_nwp_event.ctx);
cortexm_isr_end();
}
@ -77,9 +89,10 @@ void _irq_event(void *args) {
*/
void isr_nwp(void *arg)
{
DEBUG("%s()\n", __FUNCTION__);
// DEBUG("%s()\n", __FUNCTION__);
// cc3100_t *dev = (cc3100_t *)arg;
mask_nwp_rx_irqn();
// execute default handler
if (_dev->netdev.netdev.event_callback) {
_dev->netdev.netdev.event_callback(&_dev->netdev.netdev,
@ -103,6 +116,21 @@ static inline int opt_state(void *buf, bool cond)
return sizeof(netopt_enable_t);
}
char rcv_thread_stack[THREAD_STACKSIZE_MAIN];
void *rcv_thread(void *arg)
{
while (true) {
DEBUG("[cc31xx] received frame called");
// _nwp_send_raw_frame(_dev, _dev->sock_id, &RawData_Ping,
// sizeof(RawData_Ping),
// SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
_nwp_req_rcv_frame(_dev, _dev->sock_id, 0);
thread_yield();
}
// _nwp_req_rcv_frame
}
/**
* @brief cc3100_init performs NWP initialization leaving the device ready for
* future commands after this call returns
@ -117,7 +145,7 @@ static int _init(netdev_t *netdev)
DEBUG("[cc3100] init %d\n", dev->params.spi);
/* if we are on a CC32xx platform the NWP has its own interrupt
so create and register a RIOT irq_event
so create and register a RIOT irq_event
*/
_irq_nwp_event.isr = isr_nwp;
_irq_nwp_event.ctx = &dev;
@ -125,6 +153,10 @@ static int _init(netdev_t *netdev)
/* store static reference to the dev for isr callback */
_dev = dev;
/* acquire spi connection */
spi_acquire(_dev->params.spi, SPI_CS_UNDEF, SPI_SUB_MODE_0,
_dev->params.spi_clk);
cc3100_nwp_graceful_power_off();
DEBUG("[cc3100] power off completed\n");
@ -134,43 +166,183 @@ static int _init(netdev_t *netdev)
/* setup the nwp */
_nwp_setup(dev);
while (true) {
_nwp_send_raw_frame(dev, dev->sock_id, &RawData_Ping, sizeof(RawData_Ping), SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
}
// while (true) {
// _nwp_send_raw_fragments(_dev, _dev->sock_id, sizeof(RawData_Ping),
// SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
// DEBUG("Transmit fragment\n");
// cc31xx_send_to_nwp(dev, RawData_Ping, sizeof(RawData_Ping) - 8);
// // DEBUG("Transmit fragment\n");
// cc31xx_send_to_nwp(dev, &RawData_Ping[sizeof(RawData_Ping) - 9], 8);
// }
// while (true) {
// _nwp_send_raw_frame(_dev, _dev->sock_id, RawData_Ping,
// sizeof(RawData_Ping),
// SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
// }
// _nwp_set_mac_filter(dev, dev->netdev.addr);
// while (true) {
// DEBUG("[cc31xx]: reading frames \n");
// size_t len = _nwp_read_raw_frame(_dev, _dev->sock_id,
// sharedBuffer,
// sizeof(sharedBuffer), 0);
// #if ENABLE_DEBUG
// DEBUG("[cc31xx]: transceiver mode \n");
// #if defined(MODULE_OD)
// od_hex_dump(sharedBuffer, sizeof(sharedBuffer),
// OD_WIDTH_DEFAULT);
// #endif
// #endif
// }
/* configure filter for the current device */
#ifdef CPU_CC3200
ROM_IntRegister(INT_NWPIC, (void *)isr_nwp);
NVIC_SetPriority(NWPIC_IRQn, 2);
NVIC_ClearPendingIRQ(NWPIC_IRQn);
NVIC_EnableIRQ(NWPIC_IRQn);
#else
DEBUG("NON CC3200 board requires custom setup");
#endif
/* trigger receive */
// rcv_thread(NULL);
/* create receive thread */
thread_create(rcv_thread_stack, sizeof(rcv_thread_stack),
THREAD_PRIORITY_MAIN - 1, THREAD_CREATE_STACKTEST, rcv_thread,
NULL, "rcv_thread");
return 0;
}
static void _isr(netdev_t *netdev)
{
puts("ISR called");
cc31xx_read_cmd_header(_dev, &_cmd_header);
cc3100_cmd_handler(_dev, &_cmd_header);
/* notify netdev of finished isr */
netdev->event_callback(netdev, NETDEV_EVENT_RX_COMPLETE);
}
static int _send(netdev_t *netdev, const iolist_t *iolist)
{
cc3100_t *dev = (cc3100_t *)netdev;
int pkt_len = 0;
cc3100_t *dev = (cc3100_t *)netdev;
size_t pkt_len = 0;
/* send items in a packet one after the other */
// TODO: pack multiple packets into one packet
for (const iolist_t *iol = iolist; iol; iol = iol->iol_next) {
pkt_len += iol->iol_len;
_nwp_send_raw_frame(dev, dev->sock_id, iol->iol_base, iol->iol_len, SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
}
/* transmit raw frame header with total length */
_nwp_send_raw_frame(dev, dev->sock_id, NULL, pkt_len,
SL_RAW_RF_TX_PARAMS(WIFI_CHANNEL, 1, 0, 0));
/* transmit payload */
// spi_acquire(dev->params.spi, SPI_CS_UNDEF, SPI_SUB_MODE_0,
// dev->params.spi_clk);
for (const iolist_t *iol = iolist; iol; iol = iol->iol_next) {
#if ENABLE_DEBUG
DEBUG("[cc31xx]: transmitting %d byte \n", iol->iol_len);
#if defined(MODULE_OD)
od_hex_dump(iol->iol_base, iol->iol_len, OD_WIDTH_DEFAULT);
#endif
#endif
cc31xx_send_to_nwp(dev, iol->iol_base, iol->iol_len);
}
// spi_release(dev->params.spi);
// rcv_thread(NULL);
DEBUG("[cc31xx] transmission completed \n");
return 0;
}
static int _recv(netdev_t *netdev, void *buf, size_t len, void *info)
{
cc3100_t *dev = (cc3100_t *)netdev;
int16_t size = _nwp_read_raw_frame(dev, dev->sock_id, buf, len, 0);
return size;
/* failed driver read case */
if (_cmd_header.GenHeader.Opcode == 0) {
/* request a new frame */
_nwp_req_rcv_frame(dev, dev->sock_id, 0);
return 0;
}
/* check if data command came from NWP */
if (_cmd_header.GenHeader.Opcode == 0x100a) {
size_t size =
((_cmd_header.GenHeader.Len - sizeof(_ti_header)) + 3) & (~3);
/* netdev interface may call _recv to estimate package
size */
if (len == 0) {
if (size == 0) {
// spi_acquire(dev->params.spi, SPI_CS_UNDEF, SPI_SUB_MODE_0,
// dev->params.spi_clk);
/* read TI proprietary header */
cc3100_read_from_nwp(dev, &_ti_header, sizeof(_ti_header));
// spi_release(dev->params.spi);
// rcv_thread(NULL);
}
return size;
}
/* read socket info */
_SocketResponse_t sock_resp = { 0 };
cc3100_read_from_nwp(dev, &sock_resp, sizeof(_SocketResponse_t));
DEBUG("[cc31xx] read frame body status/len %d \n",
sock_resp.statusOrLen);
int16_t remainder = sock_resp.statusOrLen;
/* read TI proprietary header */
cc3100_read_from_nwp(dev, &_ti_header, sizeof(_ti_header));
/* set packet status information */
// ((netdev_radio_rx_info *)info)->rssi = _ti_header.rssi;
if (buf == NULL) {
// spi_release(dev->params.spi);
// rcv_thread(NULL);
return 0;
}
/* payload can sometimes be smaller then expected */
if (remainder < (int16_t)len) {
cc3100_read_from_nwp(dev, buf, remainder);
remainder = 0;
} else {
remainder -= len;
// DEBUG("NWP: Read payload %d bytes \n", len);
if (len > 0 && remainder >= 0) {
cc3100_read_from_nwp(dev, buf, len);
}
}
/* make sure the connection is read to the end */
if (len % 4 > 0) {
cc3100_read_from_nwp(dev, sharedBuffer, 4 - (len % 4));
}
// /* read all remaining data */
// if (remainder > 0) {
// cc3100_read_from_nwp(dev, sharedBuffer, remainder);
// }
// // rcv_thread(NULL);
#if ENABLE_DEBUG
DEBUG("[cc31xx] recv frame rssi=(%d), speed=(%d)\n", _ti_header.rssi,
_ti_header.rate);
#if defined(MODULE_OD)
od_hex_dump(buf, len, OD_WIDTH_DEFAULT);
#endif
#endif
// spi_release(dev->params.spi);
return _cmd_header.GenHeader.Len;
}
return 0;
}
static int _get(netdev_t *netdev, netopt_t opt, void *val, size_t max_len)

130
drivers/cc3100/cc3100_nwp_com.c
View File

@ -539,7 +539,8 @@ int16_t _nwp_sock_create(cc3100_t *dev, int16_t domain, int16_t type,
DEBUG("[cc31xx] socket open ID=%d Status=%d \n", m.res.sd,
m.res.statusOrLen);
if (m.res.statusOrLen < 0) {
DEBUG("[cc31xx] failed to open socket status(%d) \n", m.res.statusOrLen);
DEBUG("[cc31xx] failed to open socket status(%d) \n",
m.res.statusOrLen);
#if ENABLE_DEBUG
switch (m.res.statusOrLen) {
case SL_CONNECTION_PENDING:
@ -553,7 +554,7 @@ int16_t _nwp_sock_create(cc3100_t *dev, int16_t domain, int16_t type,
}
/**
* @brief
* @brief receive a frame from NWP blockingly
*
* @param dev
* @param sock
@ -574,10 +575,10 @@ int16_t _nwp_read_raw_frame(cc3100_t *dev, int16_t sock, void *buf,
m.req.FamilyAndFlags = options & 0x0F;
cc31xx_nwp_msg_t msg = {
.opcode = SL_OPCODE_SOCKET_RECV,
// .RespOpcode = SL_OPCODE_SOCKET_RECVASYNCRESPONSE,
.desc_buf = &m,
.desc_len = sizeof(_sendRecvCommand_t),
.opcode = SL_OPCODE_SOCKET_RECV,
.resp_opcode = SL_OPCODE_SOCKET_RECVASYNCRESPONSE,
.desc_buf = &m,
.desc_len = sizeof(_sendRecvCommand_t),
};
cc31xx_nwp_rsp_t res = {
@ -594,6 +595,38 @@ int16_t _nwp_read_raw_frame(cc3100_t *dev, int16_t sock, void *buf,
return m.res.statusOrLen;
}
/**
* @brief request the NWP to read the next Wi-Fi frame
*
* @param dev
* @param sock
* @param options
* @return int16_t
*/
int16_t _nwp_req_rcv_frame(cc3100_t *dev, int16_t sock, int16_t options)
{
/* create data object */
cc31xx_cmd_raw_sock_t m = { 0 };
/* set socket informations */
m.req.sd = sock;
m.req.StatusOrLen = IEEE80211_FRAME_LEN_MAX + sizeof(_ti_header);
m.req.FamilyAndFlags = options & 0x0F;
cc31xx_nwp_msg_t msg = {
.opcode = SL_OPCODE_SOCKET_RECV,
// .RespOpcode = SL_OPCODE_SOCKET_RECVASYNCRESPONSE,
.desc_buf = &m,
.desc_len = sizeof(_sendRecvCommand_t),
};
if (cc31xx_send_nwp_cmd(dev, &msg, NULL) != 0) {
DEBUG("ERR: failed to send NWP cmd (0x%x) \n", msg.opcode);
}
return 0;
}
int16_t _nwp_send_frame_to(cc3100_t *dev, int16_t sock, void *buf, uint16_t len,
int16_t flags, SlSockAddr_t *to, uint16_t toLen)
{
@ -635,7 +668,6 @@ int16_t _nwp_send_frame_to(cc3100_t *dev, int16_t sock, void *buf, uint16_t len,
int16_t _nwp_send_raw_frame(cc3100_t *dev, int16_t sock, void *buf, size_t len,
int16_t options)
{
DEBUG("%s() packet_len = %d \n", __FUNCTION__, len);
// TODO: add sync for multiple sockets for now only one socket is
// supported check mutex
_sendRecvCommand_t data = { 0 };
@ -663,7 +695,10 @@ int16_t _nwp_send_raw_frame(cc3100_t *dev, int16_t sock, void *buf, size_t len,
data.sd = (uint8_t)sock;
data.FamilyAndFlags |= options & 0x0F;
msg.payload_buf = (uint8_t *)(buf + bufOffset);
/* if buf is null the transmission is handled externally */
if (buf != NULL) {
msg.payload_buf = (uint8_t *)(buf + bufOffset);
}
// compute package lan either max package len or remainder
msg.payload_len =
@ -673,10 +708,6 @@ int16_t _nwp_send_raw_frame(cc3100_t *dev, int16_t sock, void *buf, size_t len,
// increment buffer offset
bufOffset += packetLen;
DEBUG("Sending package len=%d chunk %d of %d\n", msg.payload_len,
i,
chunksCount);
// send socket data
if (cc31xx_send_nwp_cmd(dev, &msg, NULL) != 0) {
DEBUG("ERR: failed to send SOCK data");
@ -689,11 +720,47 @@ int16_t _nwp_send_raw_frame(cc3100_t *dev, int16_t sock, void *buf, size_t len,
return 0;
}
int16_t _nwp_set_wifi_filter(cc3100_t *dev, uint8_t filterOptions,
uint8_t *inBuf, uint16_t bufLen)
int16_t _nwp_send_raw_fragments(cc3100_t *dev, int16_t sock, size_t len,
int16_t options)
{
// TODO: add sync for multiple sockets for now only one socket is
// supported check mutex
_sendRecvCommand_t data = { 0 };
/* compute packet len based on socket type */
uint32_t optionsCopy = options;
data.sd = (uint8_t)sock;
data.FamilyAndFlags |= options & 0x0F;
data.StatusOrLen = len;
// fast ceil without math library
// printf("Split into %d chunks \n", chunksCount);
// create request response objects
cc31xx_nwp_msg_t msg = {
.opcode = SL_OPCODE_SOCKET_SEND,
// // .RespOpcode = SL_OPCODE_DEVICE_DEVICEASYNCDUMMY,
.desc_buf = &data,
.desc_len = sizeof(_sendRecvCommand_t),
.payload_hdr_buf = &optionsCopy,
.payload_hdr_len = sizeof(uint32_t),
};
msg.payload_len = len;
if (cc31xx_send_nwp_cmd(dev, &msg, NULL) != 0) {
DEBUG("ERR: failed to send SOCK data");
return -1;
}
return 0;
}
int16_t _nwp_set_wifi_filter(cc3100_t *dev, uint8_t filter_opt, uint8_t *inBuf,
uint16_t bufLen)
{
cc31xx_cmd_set_rx_filter_t m = { 0 };
m.req.RxFilterOperation = filterOptions;
m.req.RxFilterOperation = filter_opt;
m.req.InputBufferLength = bufLen;
// create msg struct
cc31xx_nwp_msg_t msg = {
@ -715,6 +782,9 @@ int16_t _nwp_set_wifi_filter(cc3100_t *dev, uint8_t filterOptions,
printf("[cc31xx] failed to set Rx Filter \n");
return -1;
}
DEBUG("[cc31xx] filter set retuned %d \n", m.res.Status);
return m.res.Status;
}
@ -758,3 +828,33 @@ int16_t _nwp_set_sock_opt(cc3100_t *dev, uint16_t sock, uint16_t level,
}
return m.res.statusOrLen;
}
int16_t _nwp_set_mac_filter(cc3100_t *dev, uint8_t *addr)
{
_WlanRxFilterAddCommand_t cmd;
/* create header filter */
cmd.Trigger.ParentFilterID = 0;
cmd.Trigger.Trigger = NO_TRIGGER;
cmd.Trigger.TriggerArgConnectionState.IntRepresentation =
RX_FILTER_CONNECTION_STATE_STA_NOT_CONNECTED;
cmd.Trigger.TriggerArgRoleStatus.IntRepresentation =
RX_FILTER_ROLE_PROMISCUOUS;
cmd.RuleType = HEADER;
cmd.Rule.HeaderType.RuleHeaderfield = MAC_DST_ADDRESS_FIELD;
/* set mac address */
memcpy(cmd.Rule.HeaderType.RuleHeaderArgsAndMask.RuleHeaderArgs
.RxFilterDB6BytesRuleArgs[0],
addr, IEEE80211_ADDRESS_LEN);
memset(cmd.Rule.HeaderType.RuleHeaderArgsAndMask.RuleHeaderArgsMask, 0xFF,
IEEE80211_ADDRESS_LEN);
/* set compare function */
cmd.Rule.HeaderType.RuleCompareFunc = COMPARE_FUNC_NOT_EQUAL_TO;
cmd.Action.ActionType.IntRepresentation = RX_FILTER_ACTION_DROP;
cmd.FilterFlags.IntRepresentation = RX_FILTER_BINARY;
return _nwp_set_wifi_filter(dev, RX_FILTER_BINARY, (uint8_t *)&cmd,
sizeof(cmd));
}

42
drivers/cc3100/include/cc3100_internal.h
View File

@ -56,6 +56,9 @@ extern "C" {
#define REQUEST_QUEUE_SIZE (2)
// TODO: finetune this shared buffer and maybe move it to dev
static uint8_t sharedBuffer[512];
/* RX Irqn handler type */
typedef void (*cc3100_rx_irqn_handler)(void);
#define cc3100_rx_irqn_handler cc3100_rx_irqn_handler
@ -68,32 +71,39 @@ typedef struct cc3100_drv_con_info_t {
bool connected;
} cc3100_drv_con_info_t;
typedef struct {
uint8_t rate;
uint8_t channel;
int8_t rssi;
uint8_t padding;
uint32_t timestamp;
} cc31xx_ti_frame_header_t;
/**
* @brief DriverMessage is used to send a message to the NWP. Below is a simple
* diagram of a message to the NWP. Each block is transmitted a separate
* @brief DriverMessage is used to send a message to the NWP. Below is a
* simple diagram of a message to the NWP. Each block is transmitted a
* separate
* +---------------------------+
* | |
* | Msg Header | 4 byte (OPCODE + length)
* | |
* +---------------------------+
* | |
* | Cmd Description | n * 4 byte (length set by cmdDescLen)
* | (optional) |
* | |
* | Cmd Description | n * 4 byte (length set by
* cmdDescLen) | (optional) | | |
* +---------------------------+
* | |
* | Payload Header | n * 4 byte (length set by payloadLen)
* | (optional) |
* | |
* | Payload Header | n * 4 byte (length set by
* payloadLen) | (optional) | | |
* +---------------------------+
* | |
* | Payload | n * 4 byte (length set by payloadLen)
* | (optional) |
* | |
* | Payload | n * 4 byte (length set by
* payloadLen) | (optional) | | |
* +---------------------------+
*/
typedef struct {
uint16_t opcode; /**< specifies opcode & total command size */
uint16_t resp_opcode;
bool receiveFlagsViaRxPayload;
void *desc_buf; /**< command description */
@ -156,10 +166,14 @@ static cc31xx_nwp_queue_t _nwp_com = {
/**
* @brief used to notify blocking methods of a isr
*
*
*/
static uint8_t _cc31xx_isr_state = 0;
/* static header buffer */
static cc3100_nwp_resp_header_t _cmd_header = {};
static cc31xx_ti_frame_header_t _ti_header = {};
/**
* @brief mask and unmask NWP data interrupt
*
@ -173,7 +187,7 @@ static inline void unmask_nwp_rx_irqn(void)
(*(unsigned long *)N2A_INT_MASK_CLR) = 0x1;
}
void cc3100_cmd_handler(cc3100_t *dev, cc3100_nwp_resp_header_t *header);
int cc3100_read_from_nwp(cc3100_t *dev, void *buf, int len);
void cc3100_nwp_graceful_power_off(void);
void cc3100_nwp_power_on(void);
void cc3100_nwp_power_off(void);
@ -186,7 +200,7 @@ void cc31xx_send_header(cc3100_t *dev, cc3100_nwp_header_t *header);
int cc31xx_read_cmd_header(cc3100_t *dev, cc3100_nwp_resp_header_t *buf);
uint16_t _nwp_setup(cc3100_t *dev);
// int cc3100_read_from_nwp(void *buf, int len);
// int cc31xx_send_to_nwp(cc3100_t *dev, const void *buf, int len);
int cc31xx_send_to_nwp(cc3100_t *dev, const void *buf, int len);
#ifdef __cplusplus
}
#endif

8
drivers/cc3100/include/cc3100_nwp_com.h
View File

@ -21,15 +21,19 @@ int16_t _nwp_sock_create(cc3100_t *dev, int16_t domain, int16_t type,
int16_t _nwp_set_sock_opt(cc3100_t *dev, uint16_t sock, uint16_t level,
uint16_t optionName, void *optionVal,
uint8_t optionLen);
int16_t _nwp_set_wifi_filter(cc3100_t *dev, uint8_t filterOptions,
uint8_t *inBuf, uint16_t bufLen);
int16_t _nwp_set_wifi_filter(cc3100_t *dev, uint8_t filter_opt, uint8_t *inBuf,
uint16_t bufLen);
int16_t _nwp_send_raw_frame(cc3100_t *dev, int16_t sock, void *buf, int16_t len,
int16_t options);
int16_t _nwp_send_raw_fragments(cc3100_t *dev, int16_t sock, size_t len,
int16_t options);
int16_t _nwp_send_frame_to(cc3100_t *dev, int16_t sock, void *buf, uint16_t len,
int16_t flags, SlSockAddr_t *to, uint16_t toLen);
int16_t _nwp_read_raw_frame(cc3100_t *dev, int16_t sock, void *buf,
int16_t bufLen, int16_t options);
int16_t _nwp_req_rcv_frame(cc3100_t *dev, int16_t sock, int16_t options);
int16_t _nwp_set_wifi_policy(cc3100_t *dev, uint8_t type, uint8_t policy);
int16_t _nwp_del_profile(cc3100_t *dev, int16_t index);
int16_t _nwp_get_profile(cc3100_t *dev, int16_t index);
int16_t _nwp_set_mac_filter(cc3100_t *dev, uint8_t *addr);
int16_t _nwp_profile_add(cc3100_t *dev, WifiProfileConfig *conf);

2
drivers/include/cc3100.h
View File

@ -33,7 +33,7 @@
extern "C" {
#endif
#define WIFI_CHANNEL (7U)
#define WIFI_CHANNEL (11U)
/**
* @brief Struct holding all parameters needed for device initialization

20
examples/wifi/main.c
View File

@ -4,16 +4,16 @@
#include "vendor/rom.h"
#include "xtimer.h"
#include "msg.h"
#include "net/gnrc.h"
#include "net/gnrc/ipv6.h"
#include "net/gnrc/netif.h"
#include "net/gnrc/netif/hdr.h"
#include "net/gnrc/udp.h"
#include "net/gnrc/pktdump.h"
#include "msg.h"
#include "shell.h"
#include "net/gnrc/udp.h"
#include "periph/gpio.h"
#include "shell.h"
#include "xtimer.h"
#define ENABLE_DEBUG (1)
#include "debug.h"
@ -29,18 +29,22 @@ int test(int argc, char **argv)
static const shell_command_t shell_commands[] = { { "test", "test shell",
test } };
/* Forward declarations */
int16_t start_pairing(int16_t sd);
extern void send(char *addr_str, char *port_str, char *data, unsigned int num,
unsigned int delay);
// TODO: finetune this shared buffer and maybe move it to dev
int main(void)
{
int16_t status = 0;
printf("You are running RIOT on a(n) %s board.\n", RIOT_BOARD);
// while (true) {
// DEBUG("What is the time? \n");
// DEBUG("time: %lu \n", xtimer_now_usec());
// }
send("2001:0db8:85a3:0000:0000:8a2e:0370:7334", "8080", "TEST TEST TEST TEST ", 100, 10000);
send("2001:0db8:85a3:0000:0000:8a2e:0370:7334", "8080",
"TEST TEST TEST TEST ", 100, 10000);
/* start shell */
// printf("All up, running the shell now\n");